Merge pull request #1124 from mmicko/json_ports
[yosys.git] / backends / ilang /
2019-06-21 Eddie HungMerge pull request #1085 from YosysHQ/eddie/shregmap_im...
2019-06-20 Clifford WolfMerge branch 'unpacked_arrays' of https://github.com...
2019-06-19 Clifford WolfMerge pull request #1100 from bwidawsk/home
2019-06-18 Ben WidawskySupport filename rewrite in backends
2019-06-13 Serge BazanskiMerge pull request #829 from abdelrahmanhosny/master
2019-06-07 Clifford WolfMerge branch 'pr_elab_sys_tasks' of https://github...
2019-05-21 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-05-08 Clifford WolfMerge pull request #991 from kristofferkoch/gcc9-warnings
2019-05-06 Clifford WolfMerge pull request #946 from YosysHQ/clifford/specify
2019-05-06 Clifford WolfAdd "real" keyword to ilang format
2019-04-01 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2019-03-19 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-03-14 Clifford WolfMerge pull request #872 from YosysHQ/clifford/pmuxfix
2019-03-14 Clifford WolfFix a syntax bug in ilang backend related to process...
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2018-02-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2018-02-03 Clifford WolfFixed gcc 7.2 "statement will never be executed" warning
2016-10-22 Clifford WolfAdded avail params to ilang format, check module params...
2016-10-14 Clifford WolfAdded $global_clock verilog syntax support for creating...
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfAdded "yosys -D" feature
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-01-31 Clifford WolfShorter "dump" options
2015-01-24 Clifford WolfAdded ENABLE_NDEBUG makefile options
2015-01-23 Clifford WolfAdded dict/pool.sort()
2015-01-01 Clifford WolfFixed memory->start_offset handling
2014-12-26 Clifford WolfReplaced std::unordered_map as implementation for Yosys...
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-09-19 Clifford WolfSorting of object names in ilang backend
2014-08-23 Clifford WolfChanged backend-api from FILE to std::ostream
2014-07-31 Clifford WolfMoved some stuff to kernel/yosys.{h,cc}, using Yosys...
2014-07-28 Clifford WolfAdded wire->upto flag for signals such as "wire [0...
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_
2014-07-25 Clifford WolfVarious RTLIL::SigSpec related code cleanups
2014-07-24 Clifford WolfReplaced more old SigChunk programming patterns
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every...
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun...
2014-07-21 Clifford WolfAdded "autoidx" statement to ilang file format
2014-03-13 Clifford WolfMerge branch 'master' of https://github.com/Siesh1oo...
2014-03-13 Clifford WolfMerged OSX fixes from Siesh1oo with some modifications
2014-02-04 Clifford WolfAdded support for dump -append
2014-01-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2013-12-28 Clifford WolfUpdated manual/command-reference-manual.tex
2013-12-04 Clifford WolfReplaced signed_parameters API with CONST_FLAG_SIGNED
2013-12-04 Clifford WolfReplaced RTLIL::Const::str with generic decoder method
2013-11-29 Clifford WolfAdded dump -m and -n options
2013-11-24 Clifford WolfAdded support for signed parameters in ilang
2013-11-24 Clifford WolfRemove auto_wire framework (smarter than the verilog...
2013-11-21 Clifford WolfMajor improvements in mem2reg and added "init" sync...
2013-11-03 Clifford WolfWrite yosys version to output files
2013-09-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-09-03 Clifford WolfAdded -selected option to various backends
2013-06-10 Clifford WolfFixed generation of newlines in "dump" output
2013-06-02 Clifford WolfAdded "dump" command (part ilang backend)
2013-02-28 Clifford WolfAdded more help messages
2013-01-05 Clifford Wolfinitial import