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Merge remote-tracking branch 'origin/master' into clifford/specify
[yosys.git]
/
backends
/
intersynth
/
intersynth.cc
2019-04-30
Benedikt Tutzer
Merge branch 'master' of https://github.com/YosysHQ...
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2019-04-22
Clifford Wolf
Merge pull request #905 from christian-krieg/feature...
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2019-04-22
Clifford Wolf
Merge pull request #941 from Wren6991/sim_lib_io_clke
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2019-04-22
Clifford Wolf
Merge branch 'master' of https://github.com/dh73/yosys_...
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2019-04-22
Clifford Wolf
Merge pull request #911 from mmicko/gowin-nobram
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2019-04-22
Clifford Wolf
Merge pull request #909 from zachjs/master
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2019-04-22
Clifford Wolf
Merge pull request #944 from YosysHQ/clifford/pmux2shiftx
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2019-04-21
Eddie Hung
Merge branch 'master' into map_cells_before_map_luts
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2019-04-21
Eddie Hung
Merge remote-tracking branch 'origin/clifford/pmux2shif...
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2019-04-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-04-20
Clifford Wolf
Merge pull request #943 from YosysHQ/clifford/whitebox
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2019-04-18
Clifford Wolf
Add "whitebox" attribute, add "read_verilog -wb"
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2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
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2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
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2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
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2018-07-21
Henner Zeller
Consistent use of 'override' for virtual methods in...
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-04-23
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-04-21
Clifford Wolf
Added "yosys -D" feature
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-09-27
Clifford Wolf
namespace Yosys
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-08-23
Clifford Wolf
Changed frontend-api from FILE to std::istream
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2014-08-23
Clifford Wolf
Changed backend-api from FILE to std::ostream
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2014-07-28
Clifford Wolf
Using log_assert() instead of assert()
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2014-07-27
Clifford Wolf
Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-26
Clifford Wolf
Merge automatic and manual code changes for new cell...
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2014-07-26
Clifford Wolf
Changed users of cell->connections_ to the new API...
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2014-07-26
Clifford Wolf
Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-24
Clifford Wolf
Replaced more old SigChunk programming patterns
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2014-07-23
Clifford Wolf
Removed RTLIL::SigSpec::optimize()
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2014-07-22
Clifford Wolf
SigSpec refactoring: using the accessor functions every...
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2014-07-22
Clifford Wolf
SigSpec refactoring: renamed chunks and width to __chun...
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2014-01-26
Clifford Wolf
Merge branch 'btor' of https://github.com/ahmedirfan198...
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2014-01-26
Clifford Wolf
Merge pull request #21 from hansiglaser/master
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2014-01-25
Johann Glaser
beautified write_intersynth
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2013-11-22
Clifford Wolf
Renamed "placeholder" to "blackbox"
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2013-11-03
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2013-11-03
Clifford Wolf
Ignore explicit unconnected ports in intersynth backend
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2013-10-24
Clifford Wolf
Fixed handling of boolean attributes (backends)
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2013-09-03
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2013-09-03
Clifford Wolf
Added -selected option to various backends
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2013-03-24
Clifford Wolf
Added -notypes option to intersynth backend
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2013-03-23
Clifford Wolf
Fixed gcc build (intersynth backend)
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2013-03-23
Clifford Wolf
Various improvements in intersynth backend
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2013-03-23
Clifford Wolf
Added intersynth backend
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