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Merge pull request #875 from YosysHQ/clifford/mutate
[yosys.git] / backends / intersynth /
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error tree | commitdiff
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master tree | commitdiff
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64 tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override tree | commitdiff
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in... tree | commitdiff
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com... tree | commitdiff
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys tree | commitdiff
2016-04-21 Clifford WolfAdded "yosys -D" feature tree | commitdiff
2015-07-02 Clifford WolfFixed trailing whitespaces tree | commitdiff
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... tree | commitdiff
2014-09-27 Clifford Wolfnamespace Yosys tree | commitdiff
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... tree | commitdiff
2014-08-23 Clifford WolfChanged frontend-api from FILE to std::istream tree | commitdiff
2014-08-23 Clifford WolfChanged backend-api from FILE to std::ostream tree | commitdiff
2014-07-28 Clifford WolfUsing log_assert() instead of assert() tree | commitdiff
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_ tree | commitdiff
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_ tree | commitdiff
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_ tree | commitdiff
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell... tree | commitdiff
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API... tree | commitdiff
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_ tree | commitdiff
2014-07-24 Clifford WolfReplaced more old SigChunk programming patterns tree | commitdiff
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::optimize() tree | commitdiff
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every... tree | commitdiff
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun... tree | commitdiff
2014-01-26 Clifford WolfMerge branch 'btor' of https://github.com/ahmedirfan198... tree | commitdiff
2014-01-26 Clifford WolfMerge pull request #21 from hansiglaser/master tree | commitdiff
2014-01-25 Johann Glaserbeautified write_intersynth tree | commitdiff
2013-11-22 Clifford WolfRenamed "placeholder" to "blackbox" tree | commitdiff
2013-11-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2013-11-03 Clifford WolfIgnore explicit unconnected ports in intersynth backend tree | commitdiff
2013-10-24 Clifford WolfFixed handling of boolean attributes (backends) tree | commitdiff
2013-09-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2013-09-03 Clifford WolfAdded -selected option to various backends tree | commitdiff
2013-03-24 Clifford WolfAdded -notypes option to intersynth backend tree | commitdiff
2013-03-23 Clifford WolfFixed gcc build (intersynth backend) tree | commitdiff
2013-03-23 Clifford WolfVarious improvements in intersynth backend tree | commitdiff
2013-03-23 Clifford WolfAdded intersynth backend tree | commitdiff