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Fix "write_xaiger", and to write each box contents into holes
[yosys.git] / backends / spice /
2019-04-30 Jim LawsonMerge remote-tracking branch 'upstream/master' tree | commitdiff
2019-04-30 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ... tree | commitdiff
2019-04-22 Eddie HungMerge remote-tracking branch 'origin/xc7srl' into xc7mux tree | commitdiff
2019-04-22 Clifford WolfMerge pull request #905 from christian-krieg/feature... tree | commitdiff
2019-04-22 Clifford WolfMerge pull request #941 from Wren6991/sim_lib_io_clke tree | commitdiff
2019-04-22 Clifford WolfMerge branch 'master' of https://github.com/dh73/yosys_... tree | commitdiff
2019-04-22 Clifford WolfMerge pull request #911 from mmicko/gowin-nobram tree | commitdiff
2019-04-22 Clifford WolfMerge pull request #909 from zachjs/master tree | commitdiff
2019-04-22 Clifford WolfMerge pull request #944 from YosysHQ/clifford/pmux2shiftx tree | commitdiff
2019-04-21 Eddie HungMerge branch 'master' into map_cells_before_map_luts tree | commitdiff
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/clifford/pmux2shif... tree | commitdiff
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl tree | commitdiff
2019-04-20 Clifford WolfMerge pull request #943 from YosysHQ/clifford/whitebox tree | commitdiff
2019-04-18 Eddie HungMerge remote-tracking branch 'origin/clifford/whitebox... tree | commitdiff
2019-04-18 Clifford WolfAdd "whitebox" attribute, add "read_verilog -wb" tree | commitdiff
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu... tree | commitdiff
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error tree | commitdiff
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master tree | commitdiff
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64 tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override tree | commitdiff
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in... tree | commitdiff
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com... tree | commitdiff
2016-05-20 Clifford WolfMerge branch 'master' of https://github.com/Kmanfi... tree | commitdiff
2016-05-20 Clifford WolfAlso escape "=" in spice output tree | commitdiff
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys tree | commitdiff
2016-04-21 Clifford WolfAdded "yosys -D" feature tree | commitdiff
2016-04-07 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys tree | commitdiff
2016-04-05 Clifford WolfFixed some typos tree | commitdiff
2016-03-07 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2016-03-02 Clifford WolfBe more conservative with net names in spice output tree | commitdiff
2015-07-02 Clifford WolfFixed trailing whitespaces tree | commitdiff
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... tree | commitdiff
2014-12-24 Clifford WolfRenamed extend() to extend_xx(), changed most users... tree | commitdiff
2014-11-09 Clifford WolfAdded log_warning() API tree | commitdiff
2014-09-27 Clifford Wolfnamespace Yosys tree | commitdiff
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... tree | commitdiff
2014-08-23 Clifford WolfChanged backend-api from FILE to std::ostream tree | commitdiff
2014-08-02 Clifford WolfNo implicit conversion from IdString to anything else tree | commitdiff
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added... tree | commitdiff
2014-07-28 Clifford WolfUsing log_assert() instead of assert() tree | commitdiff
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_ tree | commitdiff
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_ tree | commitdiff
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_ tree | commitdiff
2014-07-26 Clifford WolfMore RTLIL::Cell API usage cleanups tree | commitdiff
2014-07-26 Clifford WolfAdded RTLIL::Cell::has(portname) tree | commitdiff
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell... tree | commitdiff
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API... tree | commitdiff
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_ tree | commitdiff
2014-07-24 Clifford WolfReplaced more old SigChunk programming patterns tree | commitdiff
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every... tree | commitdiff
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun... tree | commitdiff
2013-11-24 Clifford WolfAdded "top" attribute to mark top module in hierarchy tree | commitdiff
2013-11-22 Clifford WolfRenamed "placeholder" to "blackbox" tree | commitdiff
2013-11-09 Clifford WolfSilenced a gcc warning in spice backend tree | commitdiff
2013-11-03 Clifford WolfWrite yosys version to output files tree | commitdiff
2013-10-24 Clifford WolfFixed handling of boolean attributes (backends) tree | commitdiff
2013-09-15 Clifford WolfA couple of small fixes in SPICE backend tree | commitdiff
2013-09-14 Clifford WolfAdded spice testbench to techlibs/cmos tree | commitdiff
2013-09-14 Clifford WolfAdded spice backend tree | commitdiff