Changed frontend-api from FILE to std::istream
[yosys.git] / backends / spice /
2014-08-23 Clifford WolfChanged backend-api from FILE to std::ostream
2014-08-02 Clifford WolfNo implicit conversion from IdString to anything else
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added...
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_
2014-07-26 Clifford WolfMore RTLIL::Cell API usage cleanups
2014-07-26 Clifford WolfAdded RTLIL::Cell::has(portname)
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_
2014-07-24 Clifford WolfReplaced more old SigChunk programming patterns
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every...
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun...
2013-11-24 Clifford WolfAdded "top" attribute to mark top module in hierarchy
2013-11-22 Clifford WolfRenamed "placeholder" to "blackbox"
2013-11-09 Clifford WolfSilenced a gcc warning in spice backend
2013-11-03 Clifford WolfWrite yosys version to output files
2013-10-24 Clifford WolfFixed handling of boolean attributes (backends)
2013-09-15 Clifford WolfA couple of small fixes in SPICE backend
2013-09-14 Clifford WolfAdded spice testbench to techlibs/cmos
2013-09-14 Clifford WolfAdded spice backend