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Merge pull request #1444 from btut/feature/python_wrappers/globals_and_streams
[yosys.git]
/
backends
/
spice
/
2019-09-27
Aman Goel
Merge pull request #7 from YosysHQ/master
tree
|
commitdiff
2019-06-13
Serge Bazanski
Merge pull request #829 from abdelrahmanhosny/master
tree
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commitdiff
2019-04-30
Jim Lawson
Merge remote-tracking branch 'upstream/master'
tree
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commitdiff
2019-04-30
Benedikt Tutzer
Merge branch 'master' of https://github.com/YosysHQ...
tree
|
commitdiff
2019-04-22
Eddie Hung
Merge remote-tracking branch 'origin/xc7srl' into xc7mux
tree
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commitdiff
2019-04-22
Clifford Wolf
Merge pull request #905 from christian-krieg/feature...
tree
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commitdiff
2019-04-22
Clifford Wolf
Merge pull request #941 from Wren6991/sim_lib_io_clke
tree
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commitdiff
2019-04-22
Clifford Wolf
Merge branch 'master' of https://github.com/dh73/yosys_...
tree
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commitdiff
2019-04-22
Clifford Wolf
Merge pull request #911 from mmicko/gowin-nobram
tree
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commitdiff
2019-04-22
Clifford Wolf
Merge pull request #909 from zachjs/master
tree
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commitdiff
2019-04-22
Clifford Wolf
Merge pull request #944 from YosysHQ/clifford/pmux2shiftx
tree
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commitdiff
2019-04-21
Eddie Hung
Merge branch 'master' into map_cells_before_map_luts
tree
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commitdiff
2019-04-21
Eddie Hung
Merge remote-tracking branch 'origin/clifford/pmux2shif...
tree
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commitdiff
2019-04-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
tree
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commitdiff
2019-04-20
Clifford Wolf
Merge pull request #943 from YosysHQ/clifford/whitebox
tree
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commitdiff
2019-04-18
Eddie Hung
Merge remote-tracking branch 'origin/clifford/whitebox...
tree
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commitdiff
2019-04-18
Clifford Wolf
Add "whitebox" attribute, add "read_verilog -wb"
tree
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commitdiff
2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
tree
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commitdiff
2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
tree
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commitdiff
2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
tree
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commitdiff
2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
tree
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
tree
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
tree
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commitdiff
2018-07-21
Henner Zeller
Consistent use of 'override' for virtual methods in...
tree
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commitdiff
2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
tree
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commitdiff
2016-05-20
Clifford Wolf
Merge branch 'master' of https://github.com/Kmanfi...
tree
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commitdiff
2016-05-20
Clifford Wolf
Also escape "=" in spice output
tree
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commitdiff
2016-04-23
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
tree
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commitdiff
2016-04-21
Clifford Wolf
Added "yosys -D" feature
tree
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commitdiff
2016-04-07
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
tree
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commitdiff
2016-04-05
Clifford Wolf
Fixed some typos
tree
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commitdiff
2016-03-07
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2016-03-02
Clifford Wolf
Be more conservative with net names in spice output
tree
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commitdiff
2015-07-02
Clifford Wolf
Fixed trailing whitespaces
tree
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commitdiff
2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
tree
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commitdiff
2014-12-24
Clifford Wolf
Renamed extend() to extend_xx(), changed most users...
tree
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commitdiff
2014-11-09
Clifford Wolf
Added log_warning() API
tree
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commitdiff
2014-09-27
Clifford Wolf
namespace Yosys
tree
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commitdiff
2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
tree
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commitdiff
2014-08-23
Clifford Wolf
Changed backend-api from FILE to std::ostream
tree
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commitdiff
2014-08-02
Clifford Wolf
No implicit conversion from IdString to anything else
tree
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commitdiff
2014-07-31
Clifford Wolf
Renamed port access function on RTLIL::Cell, added...
tree
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commitdiff
2014-07-28
Clifford Wolf
Using log_assert() instead of assert()
tree
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commitdiff
2014-07-27
Clifford Wolf
Refactoring: Renamed RTLIL::Design::modules to modules_
tree
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commitdiff
2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::cells to cells_
tree
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commitdiff
2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::wires to wires_
tree
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commitdiff
2014-07-26
Clifford Wolf
More RTLIL::Cell API usage cleanups
tree
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commitdiff
2014-07-26
Clifford Wolf
Added RTLIL::Cell::has(portname)
tree
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commitdiff
2014-07-26
Clifford Wolf
Merge automatic and manual code changes for new cell...
tree
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commitdiff
2014-07-26
Clifford Wolf
Changed users of cell->connections_ to the new API...
tree
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commitdiff
2014-07-26
Clifford Wolf
Renamed RTLIL::{Module,Cell}::connections to connections_
tree
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commitdiff
2014-07-24
Clifford Wolf
Replaced more old SigChunk programming patterns
tree
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commitdiff
2014-07-22
Clifford Wolf
SigSpec refactoring: using the accessor functions every...
tree
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commitdiff
2014-07-22
Clifford Wolf
SigSpec refactoring: renamed chunks and width to __chun...
tree
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commitdiff
2013-11-24
Clifford Wolf
Added "top" attribute to mark top module in hierarchy
tree
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commitdiff
2013-11-22
Clifford Wolf
Renamed "placeholder" to "blackbox"
tree
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commitdiff
2013-11-09
Clifford Wolf
Silenced a gcc warning in spice backend
tree
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commitdiff
2013-11-03
Clifford Wolf
Write yosys version to output files
tree
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commitdiff
2013-10-24
Clifford Wolf
Fixed handling of boolean attributes (backends)
tree
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commitdiff
2013-09-15
Clifford Wolf
A couple of small fixes in SPICE backend
tree
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commitdiff
2013-09-14
Clifford Wolf
Added spice testbench to techlibs/cmos
tree
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commitdiff
2013-09-14
Clifford Wolf
Added spice backend
tree
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commitdiff