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Merge pull request #1708 from rqou/coolrunner2-buf-fix
[yosys.git]
/
backends
/
verilog
/
verilog_backend.cc
2020-02-27
Claire Wolf
Merge pull request #1708 from rqou/coolrunner2-buf-fix
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2020-02-26
Miodrag Milanović
Merge pull request #1705 from YosysHQ/logger_pass
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2020-02-21
Eddie Hung
Merge pull request #1703 from YosysHQ/eddie/specify_improve
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2020-02-20
Claire Wolf
Merge pull request #1642 from jjj11x/jjj11x/sv-enum
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2020-02-13
Eddie Hung
specify: system timing checks to accept min:typ:max...
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2020-02-13
N. Engelhardt
Merge pull request #1679 from thasti/delay-parsing
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2020-02-10
Eddie Hung
Merge pull request #1670 from rodrigomelo9/master
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2020-02-10
N. Engelhardt
Merge pull request #1669 from thasti/pyosys-attrs
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2020-02-07
Eddie Hung
Merge pull request #1685 from dh73/gowin
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2020-02-07
whitequark
Merge pull request #1683 from whitequark/write_verilog...
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2020-02-06
whitequark
write_verilog: dump $mem cell attributes.
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2020-01-29
Claire Wolf
Merge branch 'vector_fix' of https://github.com/Kmanfi...
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2019-12-16
Eddie Hung
Merge pull request #1577 from gromero/for-yosys
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2019-11-22
Eddie Hung
Merge branch 'master' of github.com:YosysHQ/yosys
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2019-11-19
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-11-19
Clifford Wolf
Merge pull request #1449 from pepijndevos/gowin
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2019-11-18
Clifford Wolf
Merge pull request #1497 from YosysHQ/mwk/extract-fa-fix
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2019-11-18
whitequark
Merge pull request #1494 from whitequark/write_verilog...
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2019-11-18
whitequark
write_verilog: add -extmem option, to write split memor...
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2019-11-14
Clifford Wolf
Merge pull request #1444 from btut/feature/python_wrapp...
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2019-11-14
Clifford Wolf
Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim
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2019-11-11
Pepijn de Vos
Merge branch 'master' of https://github.com/YosysHQ...
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2019-10-27
Clifford Wolf
Merge pull request #1393 from whitequark/write_verilog...
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2019-09-27
Aman Goel
Merge pull request #7 from YosysHQ/master
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2019-09-22
whitequark
write_verilog: do not print (*init*) attributes on...
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2019-08-26
Clifford Wolf
Merge tag 'yosys-0.9'
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2019-08-25
Clifford Wolf
Merge pull request #1112 from acw1251/pyosys_sigsig_issue
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2019-08-22
Clifford Wolf
Merge pull request #1281 from mmicko/efinix
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2019-08-20
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-16
Eddie Hung
Merge branch 'eddie/abc9_refactor' into xaig_dff
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2019-08-16
Eddie Hung
Merge pull request #1250 from bwidawsk/master
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2019-08-16
Eddie Hung
Merge https://github.com/bogdanvuk/yosys into bogdanvuk...
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2019-08-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-08-12
Serge Bazanski
Merge pull request #1152 from 1138-4EB/feat-docker
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2019-08-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-10
Clifford Wolf
Merge pull request #1258 from YosysHQ/eddie/cleanup
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2019-08-09
Miodrag Milanovic
Merge remote-tracking branch 'upstream/master' into...
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2019-08-08
David Shah
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into...
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2019-08-07
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-08-07
Eddie Hung
substr() -> compare()
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2019-08-07
Eddie Hung
RTLIL::S{0,1} -> State::S{0,1}
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2019-08-07
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-07
Jim Lawson
Merge branch 'master' into firrtl_err_on_unsupported_cell
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2019-08-07
Clifford Wolf
Merge pull request #1240 from ucb-bar/firrtl-properties...
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2019-08-07
Clifford Wolf
Merge pull request #1249 from mmicko/anlogic_fix
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2019-08-07
David Shah
Merge pull request #1241 from YosysHQ/clifford/jsonfix
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2019-08-06
Eddie Hung
Use State::S{0,1}
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2019-08-06
Eddie Hung
Make liberal use of IdString.in()
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2019-08-06
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-06
Clifford Wolf
Merge pull request #1251 from YosysHQ/clifford/nmux
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2019-08-06
Clifford Wolf
Add $_NMUX_, add "abc -g cmos", add proper cmos cell...
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2019-07-25
Eddie Hung
Merge pull request #1224 from YosysHQ/xilinx_fix_ff
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2019-07-24
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-07-19
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-07-18
Eddie Hung
Merge remote-tracking branch 'origin/master' into ice40dsp
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2019-07-18
Clifford Wolf
Merge pull request #1184 from whitequark/synth-better...
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2019-07-18
Clifford Wolf
Merge pull request #1203 from whitequark/write_verilog...
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2019-07-17
Clifford Wolf
Remove old $pmux_safe code from write_verilog
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2019-07-16
whitequark
write_verilog: dump zero width constants correctly.
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2019-07-15
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-07-15
Eddie Hung
Merge branch 'master' into eddie/fix1178
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2019-07-11
Clifford Wolf
Merge pull request #1172 from whitequark/write_verilog...
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2019-07-10
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-07-10
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-07-10
Eddie Hung
Merge pull request #1148 from YosysHQ/xc7mux
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2019-07-10
Clifford Wolf
Merge pull request #1177 from YosysHQ/clifford/async
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2019-07-09
Clifford Wolf
Merge pull request #1175 from whitequark/write_verilog...
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2019-07-09
Clifford Wolf
Merge pull request #1174 from YosysHQ/eddie/fix1173
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2019-07-09
Clifford Wolf
Merge pull request #1175 from whitequark/write_verilog...
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2019-07-09
whitequark
write_verilog: fix placement of case attributes. NFC.
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2019-07-09
whitequark
write_verilog: write RTLIL::Sa aka - as Verilog ?.
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2019-07-09
Clifford Wolf
Merge pull request #1163 from whitequark/more-case...
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2019-07-09
Eddie Hung
Merge pull request #1170 from YosysHQ/eddie/fix_double_...
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2019-07-09
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-07-09
Clifford Wolf
Merge pull request #1168 from whitequark/bugpoint-processes
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2019-07-09
Clifford Wolf
Merge pull request #1169 from whitequark/more-proc...
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2019-07-09
Clifford Wolf
Merge pull request #1163 from whitequark/more-case...
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2019-07-08
whitequark
verilog_backend: dump attributes on SwitchRule.
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2019-07-08
whitequark
verilog_backend: dump attributes on CaseRule, as comments.
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2019-06-26
Eddie Hung
Merge branch 'xc7nocarrymux' of https://github.com...
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2019-06-13
Serge Bazanski
Merge pull request #829 from abdelrahmanhosny/master
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2019-06-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-06-07
Clifford Wolf
Merge branch 'pr_elab_sys_tasks' of https://github...
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2019-05-31
Eddie Hung
Merge branch 'xaig' into xc7mux
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2019-05-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-05-21
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-05-08
Clifford Wolf
Merge pull request #991 from kristofferkoch/gcc9-warnings
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2019-05-08
Clifford Wolf
Merge pull request #998 from mdaiter/get_bool_attribute...
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2019-05-07
Clifford Wolf
Fix handling of partial init attributes in write_verilo...
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2019-05-06
Clifford Wolf
Merge pull request #946 from YosysHQ/clifford/specify
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2019-05-06
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys into...
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2019-05-04
Clifford Wolf
Improve write_verilog specify support
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2019-05-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into cliff...
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2019-04-30
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-04-30
Benedikt Tutzer
Merge branch 'master' of https://github.com/YosysHQ...
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2019-04-23
Clifford Wolf
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better...
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2019-04-23
Clifford Wolf
Add $specify2/$specify3 support to write_verilog
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2019-04-23
Clifford Wolf
Add support for $assert/$assume/$cover to write_verilog
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2019-04-22
Eddie Hung
Merge pull request #914 from YosysHQ/xc7srl
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2019-04-22
Eddie Hung
Merge branch 'xaig' into xc7mux
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