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Use ABC to convert from AIGER to Verilog
[yosys.git] / backends / verilog /
2018-10-02 Clifford WolfMerge pull request #645 from daveshah1/ecp5_dram_fix tree | commitdiff
2018-10-01 Aman GoelMerge pull request #4 from YosysHQ/master tree | commitdiff
2018-09-19 Clifford WolfMerge pull request #633 from mmicko/master tree | commitdiff
2018-09-19 Clifford WolfMerge pull request #631 from acw1251/master tree | commitdiff
2018-09-18 acw1251Fixed typo in "verilog_write" help message tree | commitdiff
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error tree | commitdiff
2018-09-17 Jim LawsonMerge remote-tracking branch 'upstream/master' tree | commitdiff
2018-09-14 Clifford WolfMerge pull request #625 from aman-goel/master tree | commitdiff
2018-09-05 Clifford WolfAdd $lut support to Verilog back-end tree | commitdiff
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master tree | commitdiff
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64 tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error tree | commitdiff
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in... tree | commitdiff
2018-05-04 Clifford WolfMerge pull request #537 from mithro/yosys-vpr tree | commitdiff
2018-04-22 Clifford WolfAdd $dlatch support to write_verilog tree | commitdiff
2017-10-10 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2017-10-07 Clifford WolfAdd $shiftx support to verilog front-end tree | commitdiff
2017-10-03 Clifford WolfMerge branch 'pr_ast_const_funcs' of https://github... tree | commitdiff
2017-10-03 Clifford WolfMerge branch 'fix_shift_reduce_conflict' of https:... tree | commitdiff
2017-10-03 Clifford WolfMerge branch 'dh73-master' tree | commitdiff
2017-10-03 Clifford WolfRename "write_verilog -nobasenradix" to "write_verilog... tree | commitdiff
2017-10-01 dh73Fixed wrong declaration in Verilog backend tree | commitdiff
2017-10-01 dh73Adding Cyclone IV (E, GX), Arria 10, Cyclone V and... tree | commitdiff
2017-05-17 Clifford WolfAdd $_ANDNOT_ and $_ORNOT_ gates tree | commitdiff
2016-11-16 Clifford WolfCleanups and fixed in write_verilog regarding reg init tree | commitdiff
2016-11-03 Clifford WolfAdded hex constant support to write_verilog tree | commitdiff
2016-11-01 Clifford WolfAdde "write_verilog -renameprefix -v" tree | commitdiff
2016-08-20 Clifford WolfBugfix in partial mem write handling in verilog back-end tree | commitdiff
2016-08-18 Clifford WolfAdded missing support for mem read enable ports to... tree | commitdiff
2016-08-15 Clifford WolfFixed upto handling in verilog back-end tree | commitdiff
2016-07-30 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2016-07-30 Clifford WolfAdded "write_verilog -defparam" tree | commitdiff
2016-07-30 Clifford WolfAdded "write_verilog -nodec -nostr" tree | commitdiff
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com... tree | commitdiff
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys tree | commitdiff
2016-04-21 Clifford WolfAdded "yosys -D" feature tree | commitdiff
2016-03-14 Clifford WolfBugfix in write_verilog for RTLIL processes tree | commitdiff
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master tree | commitdiff
2015-09-25 Clifford WolfBugfixes in writing of memories as Verilog tree | commitdiff
2015-08-14 Larry DoolittleAnother block of spelling fixes tree | commitdiff
2015-08-14 Clifford WolfRe-created command-reference-manual.tex, copied some... tree | commitdiff
2015-08-14 Clifford WolfSpell check (by Larry Doolittle) tree | commitdiff
2015-07-02 Clifford WolfFixed trailing whitespaces tree | commitdiff
2015-06-09 Clifford WolfMerge branch 'verilog-backend-memV2' of github.com... tree | commitdiff
2015-06-08 luke whittlesey$mem cell in verilog backend : grouped writes by clock tree | commitdiff
2015-06-04 luke whittleseyBug fix in $mem verilog backend + changed tests/bram... tree | commitdiff
2015-05-22 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2015-05-20 Clifford WolfSome fixes for $mem in verilog back-end tree | commitdiff
2015-05-11 Clifford WolfMerge pull request #63 from wluker/verilog-backend-mem tree | commitdiff
2015-05-11 luke whittleseyFixed bug in $mem cell verilog code generation. tree | commitdiff
2015-05-10 Clifford WolfDisabled broken $mem support in verilog backend tree | commitdiff
2015-05-10 Clifford WolfMerge pull request #62 from wluker/verilog-backend-mem tree | commitdiff
2015-05-10 luke whittleseyMade changes recommended by Clifford Wolf ... tree | commitdiff
2015-05-08 luke whittleseyVerilog backend for $mem cells should now be able to... tree | commitdiff
2015-05-07 luke whittleseyAdded support for $mem cells in the verilog backend. tree | commitdiff
2015-04-09 Clifford WolfMinor fixes in handling of "init" attribute tree | commitdiff
2015-04-04 Clifford WolfAdded "init" attribute support to verilog backend tree | commitdiff
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... tree | commitdiff
2015-03-18 Clifford WolfAdded Verilog backend $dffsr support tree | commitdiff
2015-02-13 Clifford WolfFixed "write_verilog -attr2comment" handling of "*... tree | commitdiff
2015-01-23 Clifford WolfAdded dict/pool.sort() tree | commitdiff
2015-01-02 Clifford WolfCosmetic changes in verilog output format tree | commitdiff
2014-12-26 Clifford WolfReplaced std::unordered_map as implementation for Yosys... tree | commitdiff
2014-12-26 Clifford WolfAdded Yosys::{dict,nodict,vector} container types tree | commitdiff
2014-12-19 Clifford WolfAdded $dffe support to write_verilog tree | commitdiff
2014-11-07 Clifford WolfFixed generation of temp names in verilog backend tree | commitdiff
2014-10-10 Clifford WolfRenamed SIZE() to GetSize() because of name collision... tree | commitdiff
2014-09-27 Clifford Wolfnamespace Yosys tree | commitdiff
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... tree | commitdiff
2014-09-06 Clifford WolfVarious bug fixes (related to $macc model testing) tree | commitdiff
2014-09-04 Clifford WolfRemoved $bu0 cell type tree | commitdiff
2014-09-03 Clifford WolfUsing $pos models for $bu0 tree | commitdiff
2014-08-23 Clifford WolfChanged backend-api from FILE to std::ostream tree | commitdiff
2014-08-16 Clifford WolfFixed AOI/OAI expr handling in verilog backend tree | commitdiff
2014-08-16 Clifford WolfAdded additional gate types: $_NAND_ $_NOR_ $_XNOR_... tree | commitdiff
2014-08-15 Clifford WolfRenamed $_INV_ cell type to $_NOT_ tree | commitdiff
2014-08-14 Clifford WolfRefactoring of CellType class tree | commitdiff
2014-08-02 Clifford WolfBe more conservative with printing decimal numbers... tree | commitdiff
2014-08-02 Clifford WolfImproved verilog output for ordinary $mux cells tree | commitdiff
2014-08-02 Clifford WolfMore cleanups related to RTLIL::IdString usage tree | commitdiff
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added... tree | commitdiff
2014-07-28 Clifford WolfAdded support for "upto" wires to Verilog front- and... tree | commitdiff
2014-07-28 Clifford WolfUsing log_assert() instead of assert() tree | commitdiff
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_ tree | commitdiff
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_ tree | commitdiff
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_ tree | commitdiff
2014-07-26 Clifford WolfAdded RTLIL::Cell::has(portname) tree | commitdiff
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell... tree | commitdiff
2014-07-26 Clifford WolfManual fixes for new cell connections API tree | commitdiff
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API... tree | commitdiff
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_ tree | commitdiff
2014-07-25 Clifford WolfVarious RTLIL::SigSpec related code cleanups tree | commitdiff
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::optimize() tree | commitdiff
2014-07-22 Clifford WolfSigSpec refactoring: change RTLIL::SigSpec::chunks... tree | commitdiff
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every... tree | commitdiff
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun... tree | commitdiff
2014-07-20 Clifford WolfUse functions instead of always blocks for $mux/$pmux... tree | commitdiff
2014-07-19 Clifford WolfAdded support for $bu0 to verilog backend tree | commitdiff
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