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Merge pull request #1026 from YosysHQ/clifford/fix1023
[yosys.git]
/
backends
/
verilog
/
2018-10-01
Aman Goel
Merge pull request #4 from YosysHQ/master
tree
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commitdiff
2018-09-19
Clifford Wolf
Merge pull request #633 from mmicko/master
tree
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commitdiff
2018-09-19
Clifford Wolf
Merge pull request #631 from acw1251/master
tree
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commitdiff
2018-09-18
acw1251
Fixed typo in "verilog_write" help message
tree
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commitdiff
2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
tree
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commitdiff
2018-09-17
Jim Lawson
Merge remote-tracking branch 'upstream/master'
tree
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commitdiff
2018-09-14
Clifford Wolf
Merge pull request #625 from aman-goel/master
tree
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commitdiff
2018-09-05
Clifford Wolf
Add $lut support to Verilog back-end
tree
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commitdiff
2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
tree
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commitdiff
2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
tree
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
tree
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
tree
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #513 from udif/pr_reg_wire_error
tree
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commitdiff
2018-07-21
Henner Zeller
Consistent use of 'override' for virtual methods in...
tree
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commitdiff
2018-05-04
Clifford Wolf
Merge pull request #537 from mithro/yosys-vpr
tree
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commitdiff
2018-04-22
Clifford Wolf
Add $dlatch support to write_verilog
tree
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commitdiff
2017-10-10
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2017-10-07
Clifford Wolf
Add $shiftx support to verilog front-end
tree
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commitdiff
2017-10-03
Clifford Wolf
Merge branch 'pr_ast_const_funcs' of https://github...
tree
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commitdiff
2017-10-03
Clifford Wolf
Merge branch 'fix_shift_reduce_conflict' of https:...
tree
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commitdiff
2017-10-03
Clifford Wolf
Merge branch 'dh73-master'
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commitdiff
2017-10-03
Clifford Wolf
Rename "write_verilog -nobasenradix" to "write_verilog...
tree
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commitdiff
2017-10-01
dh73
Fixed wrong declaration in Verilog backend
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commitdiff
2017-10-01
dh73
Adding Cyclone IV (E, GX), Arria 10, Cyclone V and...
tree
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commitdiff
2017-05-17
Clifford Wolf
Add $_ANDNOT_ and $_ORNOT_ gates
tree
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commitdiff
2016-11-16
Clifford Wolf
Cleanups and fixed in write_verilog regarding reg init
tree
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commitdiff
2016-11-03
Clifford Wolf
Added hex constant support to write_verilog
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commitdiff
2016-11-01
Clifford Wolf
Adde "write_verilog -renameprefix -v"
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commitdiff
2016-08-20
Clifford Wolf
Bugfix in partial mem write handling in verilog back-end
tree
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commitdiff
2016-08-18
Clifford Wolf
Added missing support for mem read enable ports to...
tree
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commitdiff
2016-08-15
Clifford Wolf
Fixed upto handling in verilog back-end
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commitdiff
2016-07-30
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2016-07-30
Clifford Wolf
Added "write_verilog -defparam"
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commitdiff
2016-07-30
Clifford Wolf
Added "write_verilog -nodec -nostr"
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commitdiff
2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
tree
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commitdiff
2016-04-23
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
tree
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commitdiff
2016-04-21
Clifford Wolf
Added "yosys -D" feature
tree
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commitdiff
2016-03-14
Clifford Wolf
Bugfix in write_verilog for RTLIL processes
tree
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commitdiff
2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
tree
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commitdiff
2015-09-25
Clifford Wolf
Bugfixes in writing of memories as Verilog
tree
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commitdiff
2015-08-14
Larry Doolittle
Another block of spelling fixes
tree
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commitdiff
2015-08-14
Clifford Wolf
Re-created command-reference-manual.tex, copied some...
tree
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commitdiff
2015-08-14
Clifford Wolf
Spell check (by Larry Doolittle)
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commitdiff
2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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commitdiff
2015-06-09
Clifford Wolf
Merge branch 'verilog-backend-memV2' of github.com...
tree
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commitdiff
2015-06-08
luke whittlesey
$mem cell in verilog backend : grouped writes by clock
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commitdiff
2015-06-04
luke whittlesey
Bug fix in $mem verilog backend + changed tests/bram...
tree
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commitdiff
2015-05-22
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2015-05-20
Clifford Wolf
Some fixes for $mem in verilog back-end
tree
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commitdiff
2015-05-11
Clifford Wolf
Merge pull request #63 from wluker/verilog-backend-mem
tree
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commitdiff
2015-05-11
luke whittlesey
Fixed bug in $mem cell verilog code generation.
tree
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commitdiff
2015-05-10
Clifford Wolf
Disabled broken $mem support in verilog backend
tree
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commitdiff
2015-05-10
Clifford Wolf
Merge pull request #62 from wluker/verilog-backend-mem
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commitdiff
2015-05-10
luke whittlesey
Made changes recommended by Clifford Wolf ...
tree
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commitdiff
2015-05-08
luke whittlesey
Verilog backend for $mem cells should now be able to...
tree
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commitdiff
2015-05-07
luke whittlesey
Added support for $mem cells in the verilog backend.
tree
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commitdiff
2015-04-09
Clifford Wolf
Minor fixes in handling of "init" attribute
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commitdiff
2015-04-04
Clifford Wolf
Added "init" attribute support to verilog backend
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commitdiff
2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
tree
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commitdiff
2015-03-18
Clifford Wolf
Added Verilog backend $dffsr support
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commitdiff
2015-02-13
Clifford Wolf
Fixed "write_verilog -attr2comment" handling of "*...
tree
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commitdiff
2015-01-23
Clifford Wolf
Added dict/pool.sort()
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commitdiff
2015-01-02
Clifford Wolf
Cosmetic changes in verilog output format
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commitdiff
2014-12-26
Clifford Wolf
Replaced std::unordered_map as implementation for Yosys...
tree
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commitdiff
2014-12-26
Clifford Wolf
Added Yosys::{dict,nodict,vector} container types
tree
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commitdiff
2014-12-19
Clifford Wolf
Added $dffe support to write_verilog
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commitdiff
2014-11-07
Clifford Wolf
Fixed generation of temp names in verilog backend
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commitdiff
2014-10-10
Clifford Wolf
Renamed SIZE() to GetSize() because of name collision...
tree
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commitdiff
2014-09-27
Clifford Wolf
namespace Yosys
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commitdiff
2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
tree
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commitdiff
2014-09-06
Clifford Wolf
Various bug fixes (related to $macc model testing)
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commitdiff
2014-09-04
Clifford Wolf
Removed $bu0 cell type
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commitdiff
2014-09-03
Clifford Wolf
Using $pos models for $bu0
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commitdiff
2014-08-23
Clifford Wolf
Changed backend-api from FILE to std::ostream
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commitdiff
2014-08-16
Clifford Wolf
Fixed AOI/OAI expr handling in verilog backend
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commitdiff
2014-08-16
Clifford Wolf
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_...
tree
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commitdiff
2014-08-15
Clifford Wolf
Renamed $_INV_ cell type to $_NOT_
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commitdiff
2014-08-14
Clifford Wolf
Refactoring of CellType class
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commitdiff
2014-08-02
Clifford Wolf
Be more conservative with printing decimal numbers...
tree
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commitdiff
2014-08-02
Clifford Wolf
Improved verilog output for ordinary $mux cells
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commitdiff
2014-08-02
Clifford Wolf
More cleanups related to RTLIL::IdString usage
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commitdiff
2014-07-31
Clifford Wolf
Renamed port access function on RTLIL::Cell, added...
tree
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commitdiff
2014-07-28
Clifford Wolf
Added support for "upto" wires to Verilog front- and...
tree
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commitdiff
2014-07-28
Clifford Wolf
Using log_assert() instead of assert()
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commitdiff
2014-07-27
Clifford Wolf
Refactoring: Renamed RTLIL::Design::modules to modules_
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commitdiff
2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::cells to cells_
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commitdiff
2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::wires to wires_
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commitdiff
2014-07-26
Clifford Wolf
Added RTLIL::Cell::has(portname)
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commitdiff
2014-07-26
Clifford Wolf
Merge automatic and manual code changes for new cell...
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commitdiff
2014-07-26
Clifford Wolf
Manual fixes for new cell connections API
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commitdiff
2014-07-26
Clifford Wolf
Changed users of cell->connections_ to the new API...
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commitdiff
2014-07-26
Clifford Wolf
Renamed RTLIL::{Module,Cell}::connections to connections_
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commitdiff
2014-07-25
Clifford Wolf
Various RTLIL::SigSpec related code cleanups
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commitdiff
2014-07-23
Clifford Wolf
Removed RTLIL::SigSpec::optimize()
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commitdiff
2014-07-22
Clifford Wolf
SigSpec refactoring: change RTLIL::SigSpec::chunks...
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commitdiff
2014-07-22
Clifford Wolf
SigSpec refactoring: using the accessor functions every...
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commitdiff
2014-07-22
Clifford Wolf
SigSpec refactoring: renamed chunks and width to __chun...
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commitdiff
2014-07-20
Clifford Wolf
Use functions instead of always blocks for $mux/$pmux...
tree
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commitdiff
2014-07-19
Clifford Wolf
Added support for $bu0 to verilog backend
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commitdiff
2014-02-07
Clifford Wolf
Added $slice and $concat cell types
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