Try way that doesn't involve creating a new wire
[yosys.git] / backends / verilog /
2019-06-07 Clifford WolfMerge branch 'pr_elab_sys_tasks' of https://github...
2019-05-21 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-05-08 Clifford WolfMerge pull request #991 from kristofferkoch/gcc9-warnings
2019-05-08 Clifford WolfMerge pull request #998 from mdaiter/get_bool_attribute...
2019-05-07 Clifford WolfFix handling of partial init attributes in write_verilo...
2019-05-06 Clifford WolfMerge pull request #946 from YosysHQ/clifford/specify
2019-05-06 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-05-04 Clifford WolfImprove write_verilog specify support
2019-05-03 Eddie HungMerge remote-tracking branch 'origin/master' into cliff...
2019-04-30 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-04-30 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-04-23 Clifford WolfRename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better...
2019-04-23 Clifford WolfAdd $specify2/$specify3 support to write_verilog
2019-04-23 Clifford WolfAdd support for $assert/$assume/$cover to write_verilog
2019-04-22 Eddie HungMerge pull request #914 from YosysHQ/xc7srl
2019-04-22 Clifford WolfMerge pull request #952 from YosysHQ/clifford/fix370
2019-04-22 Clifford WolfMerge pull request #951 from YosysHQ/clifford/logdebug
2019-04-22 Clifford WolfMerge pull request #949 from YosysHQ/clifford/pmux2shim...
2019-04-22 Clifford WolfMerge pull request #953 from YosysHQ/clifford/fix948
2019-04-22 Clifford WolfAdd support for zero-width signals to Verilog back...
2019-04-22 Clifford WolfMerge pull request #905 from christian-krieg/feature...
2019-04-22 Clifford WolfMerge pull request #941 from Wren6991/sim_lib_io_clke
2019-04-22 Clifford WolfMerge branch 'master' of https://github.com/dh73/yosys_...
2019-04-22 Clifford WolfMerge pull request #911 from mmicko/gowin-nobram
2019-04-22 Clifford WolfMerge pull request #909 from zachjs/master
2019-04-22 Clifford WolfMerge pull request #944 from YosysHQ/clifford/pmux2shiftx
2019-04-21 Eddie HungMerge branch 'master' into map_cells_before_map_luts
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/clifford/pmux2shif...
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-20 Clifford WolfMerge pull request #943 from YosysHQ/clifford/whitebox
2019-04-18 Clifford WolfAdd "whitebox" attribute, add "read_verilog -wb"
2019-04-01 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-03-14 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-14 Clifford WolfMerge pull request #869 from cr1901/win-shell
2019-03-13 Clifford WolfMerge pull request #868 from YosysHQ/clifford/fixmem
2019-03-12 Clifford WolfMerge pull request #866 from YosysHQ/clifford/idstuff
2019-03-11 Clifford WolfImprove determinism of IdString DB for similar scripts
2019-03-09 Clifford WolfMerge pull request #859 from smunaut/ice40_braminit
2019-03-01 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-03-01 Clifford WolfMerge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
2019-02-28 Clifford WolfMerge pull request #834 from YosysHQ/clifford/siminit
2019-02-28 Clifford WolfAdd "write_verilog -siminit"
2019-02-28 Clifford WolfMerge pull request #794 from daveshah1/ecp5improve
2019-02-26 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-02-24 Clifford WolfMerge pull request #812 from ucb-bar/arrayhierarchyfixes
2019-02-22 Clifford WolfMerge pull request #740 from daveshah1/improve_dress
2019-02-21 Clifford WolfMerge pull request #786 from YosysHQ/pmgen
2019-02-19 Eddie HungMerge pull request #805 from eddiehung/dff_init
2019-02-18 Eddie HungMerge branch 'dff_init' into read_aiger
2019-02-17 Eddie HungInstead of INIT param on cells, use initial statement...
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into dff_init
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-02-17 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-02-15 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-02-12 Clifford WolfMerge pull request #802 from whitequark/write_verilog_a...
2019-02-11 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-02-08 Eddie HungMerge remote-tracking branch 'origin/dff_init' into...
2019-02-06 Eddie HungRemove check for cell->name[0] == '$'
2019-02-06 Eddie HungMerge branch 'dff_init' of https://github.com/eddiehung...
2019-02-06 Eddie HungRefactor
2019-02-06 Eddie Hungwrite_verilog to cope with init attr on q when -noexpr
2019-01-29 whitequarkwrite_verilog: correctly emit asynchronous transparent...
2019-01-27 Clifford WolfMerge pull request #798 from mmicko/master
2019-01-27 Clifford WolfMerge pull request #800 from whitequark/write_verilog_t...
2019-01-27 Clifford WolfMerge branch 'whitequark-write_verilog_keyword'
2019-01-27 whitequarkwrite_verilog: write $tribuf cell as ternary.
2019-01-27 whitequarkwrite_verilog: escape names that match SystemVerilog...
2019-01-15 Clifford WolfFix handling of $shiftx in Verilog back-end
2019-01-02 Clifford WolfMerge pull request #770 from whitequark/opt_expr_cmp
2019-01-02 Clifford WolfMerge pull request #755 from Icenowy/anlogic-dram-init
2019-01-02 Clifford WolfMerge pull request #750 from Icenowy/anlogic-ff-init
2019-01-02 Clifford WolfMerge pull request #773 from whitequark/opt_lut_elim_fixes
2019-01-02 Clifford WolfMerge pull request #772 from whitequark/synth_lut
2019-01-02 Clifford WolfMerge pull request #771 from whitequark/techmap_cmp2lut
2019-01-02 Clifford WolfMerge pull request #769 from whitequark/typos
2019-01-02 whitequarkFix typographical and grammatical errors and inconsiste...
2018-12-18 Jim LawsonMerge remote-tracking branch 'upstream/master'
2018-12-17 Clifford WolfMerge pull request #746 from Icenowy/anlogic-dram
2018-12-17 Clifford WolfMerge pull request #742 from whitequark/changelog
2018-12-17 Clifford WolfMerge pull request #741 from whitequark/ilang_slice_sigspec
2018-12-17 Clifford WolfMerge pull request #744 from whitequark/write_verilog_...
2018-12-16 whitequarkwrite_verilog: handle the $shift cell.
2018-12-16 Clifford WolfMerge pull request #736 from whitequark/select_assert_list
2018-12-16 Clifford WolfMerge pull request #704 from webhat/feature/fix-awk
2018-12-16 whitequarkwrite_verilog: add a missing newline.
2018-12-16 Clifford WolfMerge pull request #738 from smunaut/issue_737
2018-12-16 Clifford WolfMerge pull request #735 from daveshah1/trifixes
2018-12-16 Clifford WolfMerge pull request #724 from whitequark/equiv_opt
2018-12-16 Clifford WolfMerge pull request #734 from grahamedgecombe/fix-shuffl...
2018-12-16 Clifford WolfMerge pull request #730 from smunaut/ffssr_dont_touch
2018-12-16 Clifford WolfMerge pull request #729 from whitequark/write_verilog_i...
2018-12-07 whitequarkwrite_verilog: correctly map RTLIL `sync init`.
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram
2018-10-19 Clifford WolfMerge pull request #671 from rafaeltp/master
2018-10-18 rafaeltpadding offset info to memories
2018-10-18 rafaeltpadding offset info to memories
2018-10-17 Clifford WolfMerge pull request #638 from udif/pr_reg_wire_error
2018-10-08 acw1251Fixed typo in "verilog_write" help message
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