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Merge remote-tracking branch 'upstream/master'
[yosys.git]
/
backends
/
verilog
/
2019-02-11
Jim Lawson
Merge remote-tracking branch 'upstream/master'
tree
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commitdiff
2019-01-27
Clifford Wolf
Merge pull request #798 from mmicko/master
tree
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commitdiff
2019-01-27
Clifford Wolf
Merge pull request #800 from whitequark/write_verilog_t...
tree
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commitdiff
2019-01-27
Clifford Wolf
Merge branch 'whitequark-write_verilog_keyword'
tree
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commitdiff
2019-01-27
whitequark
write_verilog: write $tribuf cell as ternary.
tree
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commitdiff
2019-01-27
whitequark
write_verilog: escape names that match SystemVerilog...
tree
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commitdiff
2019-01-15
Clifford Wolf
Fix handling of $shiftx in Verilog back-end
tree
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #770 from whitequark/opt_expr_cmp
tree
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #755 from Icenowy/anlogic-dram-init
tree
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #750 from Icenowy/anlogic-ff-init
tree
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #773 from whitequark/opt_lut_elim_fixes
tree
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #772 from whitequark/synth_lut
tree
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #771 from whitequark/techmap_cmp2lut
tree
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #769 from whitequark/typos
tree
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commitdiff
2019-01-02
whitequark
Fix typographical and grammatical errors and inconsiste...
tree
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commitdiff
2018-12-18
Jim Lawson
Merge remote-tracking branch 'upstream/master'
tree
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commitdiff
2018-12-17
Clifford Wolf
Merge pull request #746 from Icenowy/anlogic-dram
tree
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commitdiff
2018-12-17
Clifford Wolf
Merge pull request #742 from whitequark/changelog
tree
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commitdiff
2018-12-17
Clifford Wolf
Merge pull request #741 from whitequark/ilang_slice_sigspec
tree
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commitdiff
2018-12-17
Clifford Wolf
Merge pull request #744 from whitequark/write_verilog_...
tree
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commitdiff
2018-12-16
whitequark
write_verilog: handle the $shift cell.
tree
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commitdiff
2018-12-16
Clifford Wolf
Merge pull request #736 from whitequark/select_assert_list
tree
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commitdiff
2018-12-16
Clifford Wolf
Merge pull request #704 from webhat/feature/fix-awk
tree
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commitdiff
2018-12-16
whitequark
write_verilog: add a missing newline.
tree
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commitdiff
2018-12-16
Clifford Wolf
Merge pull request #738 from smunaut/issue_737
tree
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commitdiff
2018-12-16
Clifford Wolf
Merge pull request #735 from daveshah1/trifixes
tree
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commitdiff
2018-12-16
Clifford Wolf
Merge pull request #724 from whitequark/equiv_opt
tree
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commitdiff
2018-12-16
Clifford Wolf
Merge pull request #734 from grahamedgecombe/fix-shuffl...
tree
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commitdiff
2018-12-16
Clifford Wolf
Merge pull request #730 from smunaut/ffssr_dont_touch
tree
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commitdiff
2018-12-16
Clifford Wolf
Merge pull request #729 from whitequark/write_verilog_i...
tree
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commitdiff
2018-12-07
whitequark
write_verilog: correctly map RTLIL `sync init`.
tree
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commitdiff
2018-10-19
Clifford Wolf
Merge pull request #672 from daveshah1/fix_bram
tree
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commitdiff
2018-10-19
Clifford Wolf
Merge pull request #671 from rafaeltp/master
tree
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commitdiff
2018-10-18
rafaeltp
adding offset info to memories
tree
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commitdiff
2018-10-18
rafaeltp
adding offset info to memories
tree
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commitdiff
2018-10-17
Clifford Wolf
Merge pull request #638 from udif/pr_reg_wire_error
tree
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commitdiff
2018-10-08
acw1251
Fixed typo in "verilog_write" help message
tree
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commitdiff
2018-10-02
Clifford Wolf
Merge pull request #645 from daveshah1/ecp5_dram_fix
tree
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commitdiff
2018-10-01
Aman Goel
Merge pull request #4 from YosysHQ/master
tree
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commitdiff
2018-09-19
Clifford Wolf
Merge pull request #633 from mmicko/master
tree
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commitdiff
2018-09-19
Clifford Wolf
Merge pull request #631 from acw1251/master
tree
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commitdiff
2018-09-18
acw1251
Fixed typo in "verilog_write" help message
tree
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commitdiff
2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
tree
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commitdiff
2018-09-17
Jim Lawson
Merge remote-tracking branch 'upstream/master'
tree
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commitdiff
2018-09-14
Clifford Wolf
Merge pull request #625 from aman-goel/master
tree
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commitdiff
2018-09-05
Clifford Wolf
Add $lut support to Verilog back-end
tree
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commitdiff
2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
tree
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commitdiff
2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
tree
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
tree
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
tree
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #513 from udif/pr_reg_wire_error
tree
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commitdiff
2018-07-21
Henner Zeller
Consistent use of 'override' for virtual methods in...
tree
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commitdiff
2018-05-04
Clifford Wolf
Merge pull request #537 from mithro/yosys-vpr
tree
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commitdiff
2018-04-22
Clifford Wolf
Add $dlatch support to write_verilog
tree
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commitdiff
2017-10-10
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2017-10-07
Clifford Wolf
Add $shiftx support to verilog front-end
tree
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commitdiff
2017-10-03
Clifford Wolf
Merge branch 'pr_ast_const_funcs' of https://github...
tree
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commitdiff
2017-10-03
Clifford Wolf
Merge branch 'fix_shift_reduce_conflict' of https:...
tree
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commitdiff
2017-10-03
Clifford Wolf
Merge branch 'dh73-master'
tree
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commitdiff
2017-10-03
Clifford Wolf
Rename "write_verilog -nobasenradix" to "write_verilog...
tree
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commitdiff
2017-10-01
dh73
Fixed wrong declaration in Verilog backend
tree
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commitdiff
2017-10-01
dh73
Adding Cyclone IV (E, GX), Arria 10, Cyclone V and...
tree
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commitdiff
2017-05-17
Clifford Wolf
Add $_ANDNOT_ and $_ORNOT_ gates
tree
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commitdiff
2016-11-16
Clifford Wolf
Cleanups and fixed in write_verilog regarding reg init
tree
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commitdiff
2016-11-03
Clifford Wolf
Added hex constant support to write_verilog
tree
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commitdiff
2016-11-01
Clifford Wolf
Adde "write_verilog -renameprefix -v"
tree
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commitdiff
2016-08-20
Clifford Wolf
Bugfix in partial mem write handling in verilog back-end
tree
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commitdiff
2016-08-18
Clifford Wolf
Added missing support for mem read enable ports to...
tree
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commitdiff
2016-08-15
Clifford Wolf
Fixed upto handling in verilog back-end
tree
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commitdiff
2016-07-30
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2016-07-30
Clifford Wolf
Added "write_verilog -defparam"
tree
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commitdiff
2016-07-30
Clifford Wolf
Added "write_verilog -nodec -nostr"
tree
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commitdiff
2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
tree
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commitdiff
2016-04-23
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
tree
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commitdiff
2016-04-21
Clifford Wolf
Added "yosys -D" feature
tree
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commitdiff
2016-03-14
Clifford Wolf
Bugfix in write_verilog for RTLIL processes
tree
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commitdiff
2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
tree
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commitdiff
2015-09-25
Clifford Wolf
Bugfixes in writing of memories as Verilog
tree
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commitdiff
2015-08-14
Larry Doolittle
Another block of spelling fixes
tree
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commitdiff
2015-08-14
Clifford Wolf
Re-created command-reference-manual.tex, copied some...
tree
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commitdiff
2015-08-14
Clifford Wolf
Spell check (by Larry Doolittle)
tree
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commitdiff
2015-07-02
Clifford Wolf
Fixed trailing whitespaces
tree
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commitdiff
2015-06-09
Clifford Wolf
Merge branch 'verilog-backend-memV2' of github.com...
tree
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commitdiff
2015-06-08
luke whittlesey
$mem cell in verilog backend : grouped writes by clock
tree
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commitdiff
2015-06-04
luke whittlesey
Bug fix in $mem verilog backend + changed tests/bram...
tree
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commitdiff
2015-05-22
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2015-05-20
Clifford Wolf
Some fixes for $mem in verilog back-end
tree
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commitdiff
2015-05-11
Clifford Wolf
Merge pull request #63 from wluker/verilog-backend-mem
tree
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commitdiff
2015-05-11
luke whittlesey
Fixed bug in $mem cell verilog code generation.
tree
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commitdiff
2015-05-10
Clifford Wolf
Disabled broken $mem support in verilog backend
tree
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commitdiff
2015-05-10
Clifford Wolf
Merge pull request #62 from wluker/verilog-backend-mem
tree
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commitdiff
2015-05-10
luke whittlesey
Made changes recommended by Clifford Wolf ...
tree
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commitdiff
2015-05-08
luke whittlesey
Verilog backend for $mem cells should now be able to...
tree
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commitdiff
2015-05-07
luke whittlesey
Added support for $mem cells in the verilog backend.
tree
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commitdiff
2015-04-09
Clifford Wolf
Minor fixes in handling of "init" attribute
tree
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commitdiff
2015-04-04
Clifford Wolf
Added "init" attribute support to verilog backend
tree
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commitdiff
2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
tree
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commitdiff
2015-03-18
Clifford Wolf
Added Verilog backend $dffsr support
tree
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commitdiff
2015-02-13
Clifford Wolf
Fixed "write_verilog -attr2comment" handling of "*...
tree
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commitdiff
2015-01-23
Clifford Wolf
Added dict/pool.sort()
tree
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commitdiff
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