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Merge pull request #960 from YosysHQ/eddie/equiv_opt_undef
[yosys.git]
/
backends
/
verilog
/
2019-04-22
Eddie Hung
Merge pull request #914 from YosysHQ/xc7srl
tree
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commitdiff
2019-04-22
Clifford Wolf
Merge pull request #952 from YosysHQ/clifford/fix370
tree
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commitdiff
2019-04-22
Clifford Wolf
Merge pull request #951 from YosysHQ/clifford/logdebug
tree
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commitdiff
2019-04-22
Clifford Wolf
Merge pull request #949 from YosysHQ/clifford/pmux2shim...
tree
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commitdiff
2019-04-22
Clifford Wolf
Merge pull request #953 from YosysHQ/clifford/fix948
tree
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commitdiff
2019-04-22
Clifford Wolf
Add support for zero-width signals to Verilog back...
tree
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commitdiff
2019-04-22
Clifford Wolf
Merge pull request #905 from christian-krieg/feature...
tree
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commitdiff
2019-04-22
Clifford Wolf
Merge pull request #941 from Wren6991/sim_lib_io_clke
tree
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commitdiff
2019-04-22
Clifford Wolf
Merge branch 'master' of https://github.com/dh73/yosys_...
tree
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commitdiff
2019-04-22
Clifford Wolf
Merge pull request #911 from mmicko/gowin-nobram
tree
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commitdiff
2019-04-22
Clifford Wolf
Merge pull request #909 from zachjs/master
tree
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commitdiff
2019-04-22
Clifford Wolf
Merge pull request #944 from YosysHQ/clifford/pmux2shiftx
tree
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commitdiff
2019-04-21
Eddie Hung
Merge branch 'master' into map_cells_before_map_luts
tree
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commitdiff
2019-04-21
Eddie Hung
Merge remote-tracking branch 'origin/clifford/pmux2shif...
tree
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commitdiff
2019-04-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
tree
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commitdiff
2019-04-20
Clifford Wolf
Merge pull request #943 from YosysHQ/clifford/whitebox
tree
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commitdiff
2019-04-18
Clifford Wolf
Add "whitebox" attribute, add "read_verilog -wb"
tree
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commitdiff
2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
tree
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commitdiff
2019-03-19
Eddie Hung
Merge https://github.com/YosysHQ/yosys into read_aiger
tree
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commitdiff
2019-03-14
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
tree
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commitdiff
2019-03-14
Clifford Wolf
Merge pull request #869 from cr1901/win-shell
tree
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commitdiff
2019-03-13
Clifford Wolf
Merge pull request #868 from YosysHQ/clifford/fixmem
tree
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commitdiff
2019-03-12
Clifford Wolf
Merge pull request #866 from YosysHQ/clifford/idstuff
tree
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commitdiff
2019-03-11
Clifford Wolf
Improve determinism of IdString DB for similar scripts
tree
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commitdiff
2019-03-09
Clifford Wolf
Merge pull request #859 from smunaut/ice40_braminit
tree
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commitdiff
2019-03-01
Clifford Wolf
Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
tree
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commitdiff
2019-02-28
Clifford Wolf
Merge pull request #834 from YosysHQ/clifford/siminit
tree
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commitdiff
2019-02-28
Clifford Wolf
Add "write_verilog -siminit"
tree
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commitdiff
2019-02-28
Clifford Wolf
Merge pull request #794 from daveshah1/ecp5improve
tree
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commitdiff
2019-02-24
Clifford Wolf
Merge pull request #812 from ucb-bar/arrayhierarchyfixes
tree
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commitdiff
2019-02-22
Clifford Wolf
Merge pull request #740 from daveshah1/improve_dress
tree
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commitdiff
2019-02-21
Clifford Wolf
Merge pull request #786 from YosysHQ/pmgen
tree
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commitdiff
2019-02-19
Eddie Hung
Merge pull request #805 from eddiehung/dff_init
tree
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commitdiff
2019-02-18
Eddie Hung
Merge branch 'dff_init' into read_aiger
tree
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commitdiff
2019-02-17
Eddie Hung
Instead of INIT param on cells, use initial statement...
tree
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commitdiff
2019-02-17
Eddie Hung
Merge https://github.com/YosysHQ/yosys into dff_init
tree
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commitdiff
2019-02-17
Eddie Hung
Merge https://github.com/YosysHQ/yosys into read_aiger
tree
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commitdiff
2019-02-17
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys into...
tree
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commitdiff
2019-02-12
Clifford Wolf
Merge pull request #802 from whitequark/write_verilog_a...
tree
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commitdiff
2019-02-08
Eddie Hung
Merge remote-tracking branch 'origin/dff_init' into...
tree
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commitdiff
2019-02-06
Eddie Hung
Remove check for cell->name[0] == '$'
tree
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commitdiff
2019-02-06
Eddie Hung
Merge branch 'dff_init' of https://github.com/eddiehung...
tree
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commitdiff
2019-02-06
Eddie Hung
Refactor
tree
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commitdiff
2019-02-06
Eddie Hung
write_verilog to cope with init attr on q when -noexpr
tree
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commitdiff
2019-01-29
whitequark
write_verilog: correctly emit asynchronous transparent...
tree
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commitdiff
2019-01-27
Clifford Wolf
Merge pull request #798 from mmicko/master
tree
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commitdiff
2019-01-27
Clifford Wolf
Merge pull request #800 from whitequark/write_verilog_t...
tree
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commitdiff
2019-01-27
Clifford Wolf
Merge branch 'whitequark-write_verilog_keyword'
tree
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commitdiff
2019-01-27
whitequark
write_verilog: write $tribuf cell as ternary.
tree
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commitdiff
2019-01-27
whitequark
write_verilog: escape names that match SystemVerilog...
tree
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commitdiff
2019-01-15
Clifford Wolf
Fix handling of $shiftx in Verilog back-end
tree
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #770 from whitequark/opt_expr_cmp
tree
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #755 from Icenowy/anlogic-dram-init
tree
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #750 from Icenowy/anlogic-ff-init
tree
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #773 from whitequark/opt_lut_elim_fixes
tree
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #772 from whitequark/synth_lut
tree
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #771 from whitequark/techmap_cmp2lut
tree
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #769 from whitequark/typos
tree
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commitdiff
2019-01-02
whitequark
Fix typographical and grammatical errors and inconsiste...
tree
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commitdiff
2018-12-17
Clifford Wolf
Merge pull request #746 from Icenowy/anlogic-dram
tree
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commitdiff
2018-12-17
Clifford Wolf
Merge pull request #742 from whitequark/changelog
tree
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commitdiff
2018-12-17
Clifford Wolf
Merge pull request #741 from whitequark/ilang_slice_sigspec
tree
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commitdiff
2018-12-17
Clifford Wolf
Merge pull request #744 from whitequark/write_verilog_...
tree
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commitdiff
2018-12-16
whitequark
write_verilog: handle the $shift cell.
tree
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commitdiff
2018-12-16
Clifford Wolf
Merge pull request #736 from whitequark/select_assert_list
tree
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commitdiff
2018-12-16
Clifford Wolf
Merge pull request #704 from webhat/feature/fix-awk
tree
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commitdiff
2018-12-16
whitequark
write_verilog: add a missing newline.
tree
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commitdiff
2018-12-16
Clifford Wolf
Merge pull request #738 from smunaut/issue_737
tree
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commitdiff
2018-12-16
Clifford Wolf
Merge pull request #735 from daveshah1/trifixes
tree
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commitdiff
2018-12-16
Clifford Wolf
Merge pull request #724 from whitequark/equiv_opt
tree
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commitdiff
2018-12-16
Clifford Wolf
Merge pull request #734 from grahamedgecombe/fix-shuffl...
tree
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commitdiff
2018-12-16
Clifford Wolf
Merge pull request #730 from smunaut/ffssr_dont_touch
tree
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commitdiff
2018-12-16
Clifford Wolf
Merge pull request #729 from whitequark/write_verilog_i...
tree
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commitdiff
2018-12-07
whitequark
write_verilog: correctly map RTLIL `sync init`.
tree
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commitdiff
2018-10-19
Clifford Wolf
Merge pull request #672 from daveshah1/fix_bram
tree
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commitdiff
2018-10-19
Clifford Wolf
Merge pull request #671 from rafaeltp/master
tree
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commitdiff
2018-10-18
rafaeltp
adding offset info to memories
tree
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commitdiff
2018-10-18
rafaeltp
adding offset info to memories
tree
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commitdiff
2018-10-17
Clifford Wolf
Merge pull request #638 from udif/pr_reg_wire_error
tree
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commitdiff
2018-10-02
Clifford Wolf
Merge pull request #645 from daveshah1/ecp5_dram_fix
tree
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commitdiff
2018-10-01
Aman Goel
Merge pull request #4 from YosysHQ/master
tree
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commitdiff
2018-09-19
Clifford Wolf
Merge pull request #633 from mmicko/master
tree
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commitdiff
2018-09-19
Clifford Wolf
Merge pull request #631 from acw1251/master
tree
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commitdiff
2018-09-18
acw1251
Fixed typo in "verilog_write" help message
tree
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commitdiff
2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
tree
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commitdiff
2018-09-14
Clifford Wolf
Merge pull request #625 from aman-goel/master
tree
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commitdiff
2018-09-05
Clifford Wolf
Add $lut support to Verilog back-end
tree
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commitdiff
2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
tree
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commitdiff
2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
tree
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
tree
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
tree
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #513 from udif/pr_reg_wire_error
tree
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commitdiff
2018-07-21
Henner Zeller
Consistent use of 'override' for virtual methods in...
tree
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commitdiff
2018-05-04
Clifford Wolf
Merge pull request #537 from mithro/yosys-vpr
tree
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commitdiff
2018-04-22
Clifford Wolf
Add $dlatch support to write_verilog
tree
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commitdiff
2017-10-10
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2017-10-07
Clifford Wolf
Add $shiftx support to verilog front-end
tree
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commitdiff
2017-10-03
Clifford Wolf
Merge branch 'pr_ast_const_funcs' of https://github...
tree
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commitdiff
2017-10-03
Clifford Wolf
Merge branch 'fix_shift_reduce_conflict' of https:...
tree
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commitdiff
2017-10-03
Clifford Wolf
Merge branch 'dh73-master'
tree
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