pass jny: added connection output
[yosys.git] / backends / verilog /
2022-03-28 LoftyMerge pull request #3194 from Ravenslofty/abc9-flow3mfs
2022-02-11 Miodrag MilanovićMerge pull request #3164 from zachjs/fix-ast-warn
2022-02-11 Claire XenMerge branch 'master' into clk2ff-better-names
2022-02-11 Claire XenMerge pull request #2019 from boqwxp/glift
2022-02-07 Miodrag MilanovićMerge pull request #3185 from YosysHQ/micko/co_sim
2022-01-31 Miodrag MilanovićMerge pull request #3176 from higuoxing/fix-ref-manual
2022-01-31 Marcelina Kościelnickaverilog backend: Emit a `wire` for ports as well.
2022-01-28 Marcelina KościelnickaAdd $bmux and $demux cells.
2021-12-12 Marcelina KościelnickaAdd clean_zerowidth pass, use it for Verilog output.
2021-12-12 CatherineMerge pull request #3105 from whitequark/cxxrtl-reset...
2021-12-11 CatherineMerge pull request #3103 from whitequark/write_verilog...
2021-12-11 whitequarkwrite_verilog: dump zero width sigspecs correctly.
2021-11-17 Miodrag MilanovićMerge pull request #3080 from YosysHQ/micko/init_wire
2021-11-17 Miodrag MilanovicGive initial wire unique ID, fixes #2914
2021-10-11 Claire XenMerge pull request #3039 from YosysHQ/claire/verific_aldff
2021-10-11 Claire XenMerge pull request #3040 from YosysHQ/micko/split_modul...
2021-10-09 Miodrag MilanovicSplit module ports, 20 per line
2021-10-02 Marcelina Kościelnickakernel/ff: Refactor FfData to enable FFs with async...
2021-08-10 Marcelina Kościelnickakernel/mem: Introduce transparency masks.
2021-08-01 Marcelina Kościelnickabackend/verilog: Add alternate mode for transparent...
2021-07-28 Marcelina Kościelnickabackends/verilog: Support meminit with mask.
2021-06-09 Claire XenMerge pull request #2817 from YosysHQ/claire/fixemails
2021-06-07 Claire Xenia WolfFixing old e-mail addresses and deadnames
2021-05-27 Marcelina Kościelnickabackends/verilog: Add support for memory read port...
2021-05-27 Marcelina Kościelnickabackends/verilog: Add wide port support.
2021-05-25 Marcelina Kościelnickabackends/verilog: Try to preserve mem write port priori...
2021-05-22 Marcelina Kościelnickakernel/rtlil: Extract some helpers for checking memory...
2021-02-03 whitequarkMerge pull request #2436 from dalance/fix_generate
2020-12-02 whitequarkMerge pull request #2446 from RobertBaruch/rtlil_format
2020-11-25 whitequarkMerge pull request #2452 from whitequark/rtlil-remove...
2020-11-25 Miodrag MilanovićMerge pull request #2453 from YosysHQ/mmicko/verilog_as...
2020-11-25 Miodrag MilanovicAdd verilog backend option for simple_lhs
2020-11-25 Miodrag Milanovicgenerate only simple assignments in verilog backend
2020-11-25 Claire XenMerge pull request #2133 from dh73/nodev_head
2020-11-24 Miodrag MilanovićMerge pull request #2295 from epfl-vlsc/firrtl_blackbox...
2020-10-22 N. EngelhardtMerge pull request #2403 from nakengelhardt/sim_timescale
2020-10-21 Marcelina Kościelnickaverilog_backend: Use Mem helper.
2020-10-01 clairexenMerge pull request #2378 from udif/pr_dollar_high_low
2020-10-01 clairexenMerge pull request #2380 from Xiretza/parallel-tests
2020-09-29 clairexenMerge pull request #2393 from nakengelhardt/no_const_se...
2020-09-28 N. Engelhardtwrite_verilog: emit intermediate wire for constant...
2020-09-17 clairexenMerge pull request #2329 from antmicro/arrays-fix-multi...
2020-09-17 clairexenMerge pull request #2330 from antmicro/arrays-fix-multi...
2020-08-20 clairexenMerge pull request #2344 from YosysHQ/mwk/opt_share...
2020-08-20 clairexenMerge pull request #2337 from YosysHQ/mwk/clean-keep...
2020-08-20 clairexenMerge pull request #2333 from YosysHQ/mwk/peepopt-shift...
2020-08-20 clairexenMerge pull request #2328 from YosysHQ/mwk/opt_dff-cleanup
2020-08-20 clairexenMerge pull request #2327 from YosysHQ/mwk/techmap-const...
2020-08-20 clairexenMerge pull request #2326 from YosysHQ/mwk/peeopt-muldiv...
2020-08-20 clairexenMerge pull request #2319 from YosysHQ/mwk/techmap-cellt...
2020-08-19 clairexenMerge pull request #2122 from PeterCrozier/struct_array2
2020-08-18 XiretzaRespect \A_SIGNED for $shift
2020-08-18 Claire WolfMerge branch 'const-func-block-var' of https://github...
2020-08-18 clairexenMerge pull request #2281 from zachjs/const-real
2020-07-30 Marcelina Kościelnickaverilog_backend: Add handling for all FF types.
2020-07-17 Miodrag MilanovićMerge pull request #2274 from YosysHQ/mwk/anlogic-ff-fix
2020-07-16 clairexenMerge pull request #2229 from Ravenslofty/sf2_remove_sf...
2020-07-16 clairexenMerge pull request #2273 from whitequark/write-verilog...
2020-07-16 clairexenMerge pull request #2272 from whitequark/write-verilog-sv
2020-07-16 whitequarkverilog_backend: in non-SV mode, add a trigger for...
2020-07-16 whitequarkverilog_backend: add `-sv` option, make `-o <filename...
2020-07-02 clairexenMerge pull request #2132 from YosysHQ/eddie/verific_initial
2020-06-19 whitequarkMerge pull request #2173 from whitequark/use-cxx11...
2020-06-18 whitequarkUse C++11 final/override keywords.
2020-06-08 clairexenMerge pull request #2085 from rswarbrick/select
2020-06-08 clairexenMerge pull request #2089 from rswarbrick/modports
2020-06-04 Eddie HungMerge pull request #2077 from YosysHQ/eddie/abc9_dff_im...
2020-06-04 whitequarkMerge pull request #2006 from jersey99/signed-in-rtlil...
2020-06-04 N. EngelhardtMerge pull request #2070 from hackfin/master
2020-06-04 Eddie HungMerge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes no_loop
2020-06-03 Peter CrozierMerge branch 'master' into struct
2020-06-03 Eddie HungMerge pull request #2080 from YosysHQ/eddie/fix_test_wa...
2020-05-31 clairexenMerge pull request #1862 from boqwxp/cleanup_techmap
2020-05-30 Eddie HungMerge pull request #2081 from YosysHQ/eddie/blackbox_ast
2020-05-30 clairexenMerge pull request #2018 from boqwxp/qbfsat-timeout
2020-05-29 clairexenMerge pull request #2029 from whitequark/fix-simplify...
2020-05-29 clairexenMerge pull request #1885 from Xiretza/mod-rem-cells
2020-05-28 XiretzaAdd flooring division operator
2020-05-28 XiretzaAdd flooring modulo operator
2020-04-17 whitequarkMerge pull request #1864 from boqwxp/cleanup_techmap_abc
2020-04-16 whitequarkMerge pull request #1896 from boqwxp/read_stdin_repl
2020-04-16 Claire WolfMerge pull request #1797 from epfl-vlsc/firrtl_backend_...
2020-04-16 whitequarkMerge pull request #1915 from boqwxp/dict_move_semantics
2020-04-16 whitequarkMerge pull request #1900 from Xiretza/suppress-makefile...
2020-04-15 Miodrag MilanovićMerge pull request #1894 from YosysHQ/mingw_fix
2020-04-15 Eddie HungMerge pull request #1916 from YosysHQ/eddie/kernel_make...
2020-04-15 N. EngelhardtMerge pull request #1830 from boqwxp/qbfsat
2020-04-15 David ShahMerge pull request #1897 from YosysHQ/dave/bram-rejecti...
2020-04-15 whitequarkMerge pull request #1918 from whitequark/simplify-impro...
2020-04-14 whitequarkMerge pull request #1922 from whitequark/write_cxxrtl...
2020-04-14 whitequarkMerge pull request #1921 from whitequark/write_cxxrtl...
2020-04-14 whitequarkwrite_verilog: fix precondition check.
2020-04-10 whitequarkMerge pull request #1603 from whitequark/ice40-ram_style
2020-04-08 Sahand KashaniMerge branch 'master' of github.com:YosysHQ/yosys into...
2020-04-07 Claire WolfMerge pull request #1814 from YosysHQ/mmicko/pyosys_mak...
2020-04-06 whitequarkMerge pull request #1859 from boqwxp/design_duplicate
2020-04-03 Eddie HungMerge pull request #1648 from YosysHQ/eddie/cmp2lcu
2020-04-02 Eddie HungMerge pull request #1853 from YosysHQ/eddie/fix_dynslice
2020-04-02 Eddie HungMerge pull request #1767 from YosysHQ/eddie/idstrings
2020-04-02 Eddie Hungkernel: big fat patch to use more ID::*, otherwise...
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