2018-08-15 |
Clifford Wolf | Merge pull request #513 from udif/pr_reg_wire_error |
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2018-07-21 |
Henner Zeller | Consistent use of 'override' for virtual methods in... |
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2018-05-04 |
Clifford Wolf | Merge pull request #537 from mithro/yosys-vpr |
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2018-04-22 |
Clifford Wolf | Add $dlatch support to write_verilog |
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2017-10-10 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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2017-10-07 |
Clifford Wolf | Add $shiftx support to verilog front-end |
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2017-10-03 |
Clifford Wolf | Merge branch 'pr_ast_const_funcs' of https://github... |
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2017-10-03 |
Clifford Wolf | Merge branch 'fix_shift_reduce_conflict' of https:... |
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2017-10-03 |
Clifford Wolf | Merge branch 'dh73-master' |
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2017-10-03 |
Clifford Wolf | Rename "write_verilog -nobasenradix" to "write_verilog... |
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2017-10-01 |
dh73 | Fixed wrong declaration in Verilog backend |
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2017-10-01 |
dh73 | Adding Cyclone IV (E, GX), Arria 10, Cyclone V and... |
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2017-05-17 |
Clifford Wolf | Add $_ANDNOT_ and $_ORNOT_ gates |
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2016-11-16 |
Clifford Wolf | Cleanups and fixed in write_verilog regarding reg init |
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2016-11-03 |
Clifford Wolf | Added hex constant support to write_verilog |
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2016-11-01 |
Clifford Wolf | Adde "write_verilog -renameprefix -v" |
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2016-08-20 |
Clifford Wolf | Bugfix in partial mem write handling in verilog back-end |
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2016-08-18 |
Clifford Wolf | Added missing support for mem read enable ports to... |
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2016-08-15 |
Clifford Wolf | Fixed upto handling in verilog back-end |
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2016-07-30 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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2016-07-30 |
Clifford Wolf | Added "write_verilog -defparam" |
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2016-07-30 |
Clifford Wolf | Added "write_verilog -nodec -nostr" |
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2016-07-08 |
Clifford Wolf | Merge branch 'yosys-0.5-vtr' of https://github.com... |
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2016-04-23 |
Andrew Zonenberg | Merge https://github.com/cliffordwolf/yosys |
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2016-04-21 |
Clifford Wolf | Added "yosys -D" feature |
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2016-03-14 |
Clifford Wolf | Bugfix in write_verilog for RTLIL processes |
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2015-12-07 |
Clifford Wolf | Merge pull request #108 from cseed/master |
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2015-09-25 |
Clifford Wolf | Bugfixes in writing of memories as Verilog |
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2015-08-14 |
Larry Doolittle | Another block of spelling fixes |
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2015-08-14 |
Clifford Wolf | Re-created command-reference-manual.tex, copied some... |
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2015-08-14 |
Clifford Wolf | Spell check (by Larry Doolittle) |
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2015-07-02 |
Clifford Wolf | Fixed trailing whitespaces |
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2015-06-09 |
Clifford Wolf | Merge branch 'verilog-backend-memV2' of github.com... |
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2015-06-08 |
luke whittlesey | $mem cell in verilog backend : grouped writes by clock |
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2015-06-04 |
luke whittlesey | Bug fix in $mem verilog backend + changed tests/bram... |
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2015-05-22 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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2015-05-20 |
Clifford Wolf | Some fixes for $mem in verilog back-end |
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2015-05-11 |
Clifford Wolf | Merge pull request #63 from wluker/verilog-backend-mem |
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2015-05-11 |
luke whittlesey | Fixed bug in $mem cell verilog code generation. |
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2015-05-10 |
Clifford Wolf | Disabled broken $mem support in verilog backend |
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2015-05-10 |
Clifford Wolf | Merge pull request #62 from wluker/verilog-backend-mem |
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2015-05-10 |
luke whittlesey | Made changes recommended by Clifford Wolf ... |
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2015-05-08 |
luke whittlesey | Verilog backend for $mem cells should now be able to... |
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2015-05-07 |
luke whittlesey | Added support for $mem cells in the verilog backend. |
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2015-04-09 |
Clifford Wolf | Minor fixes in handling of "init" attribute |
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2015-04-04 |
Clifford Wolf | Added "init" attribute support to verilog backend |
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2015-04-03 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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2015-03-18 |
Clifford Wolf | Added Verilog backend $dffsr support |
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2015-02-13 |
Clifford Wolf | Fixed "write_verilog -attr2comment" handling of "*... |
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2015-01-23 |
Clifford Wolf | Added dict/pool.sort() |
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2015-01-02 |
Clifford Wolf | Cosmetic changes in verilog output format |
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2014-12-26 |
Clifford Wolf | Replaced std::unordered_map as implementation for Yosys... |
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2014-12-26 |
Clifford Wolf | Added Yosys::{dict,nodict,vector} container types |
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2014-12-19 |
Clifford Wolf | Added $dffe support to write_verilog |
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2014-11-07 |
Clifford Wolf | Fixed generation of temp names in verilog backend |
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2014-10-10 |
Clifford Wolf | Renamed SIZE() to GetSize() because of name collision... |
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2014-09-27 |
Clifford Wolf | namespace Yosys |
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2014-09-22 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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2014-09-06 |
Clifford Wolf | Various bug fixes (related to $macc model testing) |
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2014-09-04 |
Clifford Wolf | Removed $bu0 cell type |
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2014-09-03 |
Clifford Wolf | Using $pos models for $bu0 |
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2014-08-23 |
Clifford Wolf | Changed backend-api from FILE to std::ostream |
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2014-08-16 |
Clifford Wolf | Fixed AOI/OAI expr handling in verilog backend |
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2014-08-16 |
Clifford Wolf | Added additional gate types: $_NAND_ $_NOR_ $_XNOR_... |
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2014-08-15 |
Clifford Wolf | Renamed $_INV_ cell type to $_NOT_ |
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2014-08-14 |
Clifford Wolf | Refactoring of CellType class |
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2014-08-02 |
Clifford Wolf | Be more conservative with printing decimal numbers... |
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2014-08-02 |
Clifford Wolf | Improved verilog output for ordinary $mux cells |
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2014-08-02 |
Clifford Wolf | More cleanups related to RTLIL::IdString usage |
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2014-07-31 |
Clifford Wolf | Renamed port access function on RTLIL::Cell, added... |
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2014-07-28 |
Clifford Wolf | Added support for "upto" wires to Verilog front- and... |
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2014-07-28 |
Clifford Wolf | Using log_assert() instead of assert() |
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2014-07-27 |
Clifford Wolf | Refactoring: Renamed RTLIL::Design::modules to modules_ |
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2014-07-26 |
Clifford Wolf | Refactoring: Renamed RTLIL::Module::cells to cells_ |
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2014-07-26 |
Clifford Wolf | Refactoring: Renamed RTLIL::Module::wires to wires_ |
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2014-07-26 |
Clifford Wolf | Added RTLIL::Cell::has(portname) |
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2014-07-26 |
Clifford Wolf | Merge automatic and manual code changes for new cell... |
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2014-07-26 |
Clifford Wolf | Manual fixes for new cell connections API |
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2014-07-26 |
Clifford Wolf | Changed users of cell->connections_ to the new API... |
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2014-07-26 |
Clifford Wolf | Renamed RTLIL::{Module,Cell}::connections to connections_ |
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2014-07-25 |
Clifford Wolf | Various RTLIL::SigSpec related code cleanups |
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2014-07-23 |
Clifford Wolf | Removed RTLIL::SigSpec::optimize() |
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2014-07-22 |
Clifford Wolf | SigSpec refactoring: change RTLIL::SigSpec::chunks... |
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2014-07-22 |
Clifford Wolf | SigSpec refactoring: using the accessor functions every... |
tree | commitdiff |
2014-07-22 |
Clifford Wolf | SigSpec refactoring: renamed chunks and width to __chun... |
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2014-07-20 |
Clifford Wolf | Use functions instead of always blocks for $mux/$pmux... |
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2014-07-19 |
Clifford Wolf | Added support for $bu0 to verilog backend |
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2014-02-07 |
Clifford Wolf | Added $slice and $concat cell types |
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2014-01-03 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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2013-12-27 |
Clifford Wolf | Added support for non-const === and !== (for miter... |
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2013-12-04 |
Clifford Wolf | Replaced signed_parameters API with CONST_FLAG_SIGNED |
tree | commitdiff |
2013-12-04 |
Clifford Wolf | Replaced RTLIL::Const::str with generic decoder method |
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2013-11-24 |
Clifford Wolf | Added proper dumping of signed/unsigned parameters... |
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2013-11-22 |
Clifford Wolf | Renamed "placeholder" to "blackbox" |
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2013-11-21 |
Clifford Wolf | Implemented $_DFFSR_ expression generator in verilog... |
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2013-11-03 |
Clifford Wolf | Write yosys version to output files |
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2013-10-24 |
Clifford Wolf | Fixed handling of boolean attributes (backends) |
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2013-10-24 |
Clifford Wolf | Fixed handling of boolean attributes (kernel) |
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2013-10-18 |
Clifford Wolf | Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_... |
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2013-10-18 |
Clifford Wolf | Added $sr, $dffsr and $dlatch cell types |
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