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Merge pull request #943 from YosysHQ/clifford/whitebox
[yosys.git] / backends / verilog /
2019-04-20 Clifford WolfMerge pull request #943 from YosysHQ/clifford/whitebox tree | commitdiff
2019-04-18 Clifford WolfAdd "whitebox" attribute, add "read_verilog -wb" tree | commitdiff
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger tree | commitdiff
2019-03-14 Clifford WolfMerge pull request #869 from cr1901/win-shell tree | commitdiff
2019-03-13 Clifford WolfMerge pull request #868 from YosysHQ/clifford/fixmem tree | commitdiff
2019-03-12 Clifford WolfMerge pull request #866 from YosysHQ/clifford/idstuff tree | commitdiff
2019-03-11 Clifford WolfImprove determinism of IdString DB for similar scripts tree | commitdiff
2019-03-09 Clifford WolfMerge pull request #859 from smunaut/ice40_braminit tree | commitdiff
2019-03-01 Clifford WolfMerge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode tree | commitdiff
2019-02-28 Clifford WolfMerge pull request #834 from YosysHQ/clifford/siminit tree | commitdiff
2019-02-28 Clifford WolfAdd "write_verilog -siminit" tree | commitdiff
2019-02-28 Clifford WolfMerge pull request #794 from daveshah1/ecp5improve tree | commitdiff
2019-02-24 Clifford WolfMerge pull request #812 from ucb-bar/arrayhierarchyfixes tree | commitdiff
2019-02-22 Clifford WolfMerge pull request #740 from daveshah1/improve_dress tree | commitdiff
2019-02-21 Clifford WolfMerge pull request #786 from YosysHQ/pmgen tree | commitdiff
2019-02-19 Eddie HungMerge pull request #805 from eddiehung/dff_init tree | commitdiff
2019-02-18 Eddie HungMerge branch 'dff_init' into read_aiger tree | commitdiff
2019-02-17 Eddie HungInstead of INIT param on cells, use initial statement... tree | commitdiff
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into dff_init tree | commitdiff
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger tree | commitdiff
2019-02-17 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into... tree | commitdiff
2019-02-12 Clifford WolfMerge pull request #802 from whitequark/write_verilog_a... tree | commitdiff
2019-02-08 Eddie HungMerge remote-tracking branch 'origin/dff_init' into... tree | commitdiff
2019-02-06 Eddie HungRemove check for cell->name[0] == '$' tree | commitdiff
2019-02-06 Eddie HungMerge branch 'dff_init' of https://github.com/eddiehung... tree | commitdiff
2019-02-06 Eddie HungRefactor tree | commitdiff
2019-02-06 Eddie Hungwrite_verilog to cope with init attr on q when -noexpr tree | commitdiff
2019-01-29 whitequarkwrite_verilog: correctly emit asynchronous transparent... tree | commitdiff
2019-01-27 Clifford WolfMerge pull request #798 from mmicko/master tree | commitdiff
2019-01-27 Clifford WolfMerge pull request #800 from whitequark/write_verilog_t... tree | commitdiff
2019-01-27 Clifford WolfMerge branch 'whitequark-write_verilog_keyword' tree | commitdiff
2019-01-27 whitequarkwrite_verilog: write $tribuf cell as ternary. tree | commitdiff
2019-01-27 whitequarkwrite_verilog: escape names that match SystemVerilog... tree | commitdiff
2019-01-15 Clifford WolfFix handling of $shiftx in Verilog back-end tree | commitdiff
2019-01-02 Clifford WolfMerge pull request #770 from whitequark/opt_expr_cmp tree | commitdiff
2019-01-02 Clifford WolfMerge pull request #755 from Icenowy/anlogic-dram-init tree | commitdiff
2019-01-02 Clifford WolfMerge pull request #750 from Icenowy/anlogic-ff-init tree | commitdiff
2019-01-02 Clifford WolfMerge pull request #773 from whitequark/opt_lut_elim_fixes tree | commitdiff
2019-01-02 Clifford WolfMerge pull request #772 from whitequark/synth_lut tree | commitdiff
2019-01-02 Clifford WolfMerge pull request #771 from whitequark/techmap_cmp2lut tree | commitdiff
2019-01-02 Clifford WolfMerge pull request #769 from whitequark/typos tree | commitdiff
2019-01-02 whitequarkFix typographical and grammatical errors and inconsiste... tree | commitdiff
2018-12-17 Clifford WolfMerge pull request #746 from Icenowy/anlogic-dram tree | commitdiff
2018-12-17 Clifford WolfMerge pull request #742 from whitequark/changelog tree | commitdiff
2018-12-17 Clifford WolfMerge pull request #741 from whitequark/ilang_slice_sigspec tree | commitdiff
2018-12-17 Clifford WolfMerge pull request #744 from whitequark/write_verilog_... tree | commitdiff
2018-12-16 whitequarkwrite_verilog: handle the $shift cell. tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #736 from whitequark/select_assert_list tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #704 from webhat/feature/fix-awk tree | commitdiff
2018-12-16 whitequarkwrite_verilog: add a missing newline. tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #738 from smunaut/issue_737 tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #735 from daveshah1/trifixes tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #724 from whitequark/equiv_opt tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #734 from grahamedgecombe/fix-shuffl... tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #730 from smunaut/ffssr_dont_touch tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #729 from whitequark/write_verilog_i... tree | commitdiff
2018-12-07 whitequarkwrite_verilog: correctly map RTLIL `sync init`. tree | commitdiff
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram tree | commitdiff
2018-10-19 Clifford WolfMerge pull request #671 from rafaeltp/master tree | commitdiff
2018-10-18 rafaeltpadding offset info to memories tree | commitdiff
2018-10-18 rafaeltpadding offset info to memories tree | commitdiff
2018-10-17 Clifford WolfMerge pull request #638 from udif/pr_reg_wire_error tree | commitdiff
2018-10-02 Clifford WolfMerge pull request #645 from daveshah1/ecp5_dram_fix tree | commitdiff
2018-10-01 Aman GoelMerge pull request #4 from YosysHQ/master tree | commitdiff
2018-09-19 Clifford WolfMerge pull request #633 from mmicko/master tree | commitdiff
2018-09-19 Clifford WolfMerge pull request #631 from acw1251/master tree | commitdiff
2018-09-18 acw1251Fixed typo in "verilog_write" help message tree | commitdiff
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error tree | commitdiff
2018-09-14 Clifford WolfMerge pull request #625 from aman-goel/master tree | commitdiff
2018-09-05 Clifford WolfAdd $lut support to Verilog back-end tree | commitdiff
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master tree | commitdiff
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64 tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error tree | commitdiff
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in... tree | commitdiff
2018-05-04 Clifford WolfMerge pull request #537 from mithro/yosys-vpr tree | commitdiff
2018-04-22 Clifford WolfAdd $dlatch support to write_verilog tree | commitdiff
2017-10-10 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2017-10-07 Clifford WolfAdd $shiftx support to verilog front-end tree | commitdiff
2017-10-03 Clifford WolfMerge branch 'pr_ast_const_funcs' of https://github... tree | commitdiff
2017-10-03 Clifford WolfMerge branch 'fix_shift_reduce_conflict' of https:... tree | commitdiff
2017-10-03 Clifford WolfMerge branch 'dh73-master' tree | commitdiff
2017-10-03 Clifford WolfRename "write_verilog -nobasenradix" to "write_verilog... tree | commitdiff
2017-10-01 dh73Fixed wrong declaration in Verilog backend tree | commitdiff
2017-10-01 dh73Adding Cyclone IV (E, GX), Arria 10, Cyclone V and... tree | commitdiff
2017-05-17 Clifford WolfAdd $_ANDNOT_ and $_ORNOT_ gates tree | commitdiff
2016-11-16 Clifford WolfCleanups and fixed in write_verilog regarding reg init tree | commitdiff
2016-11-03 Clifford WolfAdded hex constant support to write_verilog tree | commitdiff
2016-11-01 Clifford WolfAdde "write_verilog -renameprefix -v" tree | commitdiff
2016-08-20 Clifford WolfBugfix in partial mem write handling in verilog back-end tree | commitdiff
2016-08-18 Clifford WolfAdded missing support for mem read enable ports to... tree | commitdiff
2016-08-15 Clifford WolfFixed upto handling in verilog back-end tree | commitdiff
2016-07-30 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2016-07-30 Clifford WolfAdded "write_verilog -defparam" tree | commitdiff
2016-07-30 Clifford WolfAdded "write_verilog -nodec -nostr" tree | commitdiff
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com... tree | commitdiff
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys tree | commitdiff
2016-04-21 Clifford WolfAdded "yosys -D" feature tree | commitdiff
2016-03-14 Clifford WolfBugfix in write_verilog for RTLIL processes tree | commitdiff
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