Fix "write_xaiger", and to write each box contents into holes
[yosys.git] / backends /
2019-05-26 Eddie HungFix "write_xaiger", and to write each box contents...
2019-05-26 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-05-25 Clifford WolfMerge pull request #1041 from YosysHQ/clifford/fix1040
2019-05-25 Clifford WolfFix handling of offset and upto module ports in write_b...
2019-05-24 Clifford WolfAdd proper error message for btor recursion_guard
2019-05-23 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-05-23 Eddie HungMerge remote-tracking branch 'origin/eddie/opt_rmdff...
2019-05-23 Clifford WolfMerge pull request #1031 from mdaiter/optimizeLookupTab...
2019-05-22 Clifford WolfMerge pull request #1019 from YosysHQ/clifford/fix1016
2019-05-22 Clifford WolfMerge pull request #1021 from ucb-bar/fixfirrtl_shr,neg
2019-05-21 Eddie HungPad all boxes so that all input/output connections...
2019-05-21 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-05-21 Jim LawsonFix static shift operands, neg result type, minor forma...
2019-05-21 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-05-08 Clifford WolfMerge pull request #991 from kristofferkoch/gcc9-warnings
2019-05-08 Kristoffer Ellersg... Fix all warnings that occurred when compiling with...
2019-05-08 Clifford WolfMerge pull request #998 from mdaiter/get_bool_attribute...
2019-05-07 Clifford WolfFix handling of partial init attributes in write_verilo...
2019-05-06 Clifford WolfMerge pull request #946 from YosysHQ/clifford/specify
2019-05-06 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-05-06 Clifford WolfAdd "real" keyword to ilang format
2019-05-06 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-05-04 Clifford WolfImprove write_verilog specify support
2019-05-03 Eddie HungMerge remote-tracking branch 'origin/master' into cliff...
2019-05-03 Clifford WolfMerge pull request #969 from YosysHQ/clifford/pmgenstuff
2019-05-03 Clifford WolfMerge pull request #976 from YosysHQ/clifford/fix974
2019-05-02 Eddie HungMerge remote-tracking branch 'origin/clifford/pmgenstuf...
2019-05-02 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-05-02 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-05-02 Clifford WolfMerge pull request #963 from YosysHQ/eddie/synth_xilinx...
2019-05-02 Eddie HungMerge pull request #978 from ucb-bar/fmtfirrtl
2019-05-02 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-05-01 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-05-01 Jim LawsonRe-indent firrtl.cc:struct memory - no functional change.
2019-05-01 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-05-01 Clifford WolfMerge pull request #977 from ucb-bar/fixfirrtlmem
2019-05-01 Jim LawsonFix #938 - Crash occurs in case when use write_firrtl...
2019-04-30 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-04-30 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-04-26 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-04-26 Eddie HungMerge remote-tracking branch 'origin/eddie/split_shiftx...
2019-04-26 Eddie HungMerge branch 'eddie/split_shiftx' into xc7mux
2019-04-25 Eddie HungRemove topo sort no-loop assertion, with test
2019-04-23 Eddie HungFix abc9 with (* keep *) wires
2019-04-23 Clifford WolfRename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better...
2019-04-23 Clifford WolfAdd $specify2/$specify3 support to write_verilog
2019-04-23 Clifford WolfAdd support for $assert/$assume/$cover to write_verilog
2019-04-22 Eddie HungMerge pull request #914 from YosysHQ/xc7srl
2019-04-22 Eddie HungMerge branch 'xaig' into xc7mux
2019-04-22 Eddie HungTemporarily remove 'r' extension
2019-04-22 Eddie HungMerge remote-tracking branch 'origin/xc7srl' into xc7mux
2019-04-22 Eddie HungAllow POs to be PIs in XAIG
2019-04-22 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-04-22 Clifford WolfMerge pull request #952 from YosysHQ/clifford/fix370
2019-04-22 Clifford WolfMerge pull request #951 from YosysHQ/clifford/logdebug
2019-04-22 Clifford WolfMerge pull request #949 from YosysHQ/clifford/pmux2shim...
2019-04-22 Clifford WolfMerge pull request #953 from YosysHQ/clifford/fix948
2019-04-22 Clifford WolfAdd support for zero-width signals to Verilog back...
2019-04-22 Clifford WolfMerge pull request #905 from christian-krieg/feature...
2019-04-22 Clifford WolfMerge pull request #941 from Wren6991/sim_lib_io_clke
2019-04-22 Clifford WolfMerge branch 'master' of https://github.com/dh73/yosys_...
2019-04-22 Clifford WolfMerge pull request #911 from mmicko/gowin-nobram
2019-04-22 Clifford WolfMerge pull request #909 from zachjs/master
2019-04-22 Clifford WolfMerge pull request #944 from YosysHQ/clifford/pmux2shiftx
2019-04-22 Eddie HungMerge remote-tracking branch 'origin/clifford/libwb...
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/clifford/libwb...
2019-04-21 Eddie HungMerge branch 'master' into map_cells_before_map_luts
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/clifford/pmux2shif...
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-20 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-04-20 Clifford WolfMerge pull request #943 from YosysHQ/clifford/whitebox
2019-04-20 Eddie HungMerge remote-tracking branch 'origin/pmux2shiftx' into...
2019-04-20 Eddie HungMerge remote-tracking branch 'origin' into xc7srl
2019-04-20 Clifford WolfMerge pull request #942 from YosysHQ/clifford/fix931
2019-04-19 Eddie HungFixes for simple_abc9 tests
2019-04-19 Clifford WolfChange "ne" to "neq" in btor2 output
2019-04-19 Eddie HungDo not assume inst_module is always present
2019-04-19 Eddie Hungignore_boxes -> holes_mode
2019-04-19 Eddie HungRevert "write_json to not write contents (cells/wires...
2019-04-19 Eddie HungAdd flop support for write_xaiger
2019-04-19 Eddie HungSpelling
2019-04-18 Eddie HungUse new -wb flag for ABC flow
2019-04-18 Eddie Hungwrite_json to not write contents (cells/wires) of white...
2019-04-18 Eddie Hungwrite_json to not write contents (cells/wires) of white...
2019-04-18 Eddie HungMerge remote-tracking branch 'origin/clifford/whitebox...
2019-04-18 Clifford WolfAdd "whitebox" attribute, add "read_verilog -wb"
2019-04-17 Eddie HungFix $anyseq warning and cleanup
2019-04-17 Eddie HungCope with inout ports
2019-04-17 Eddie HungStop topological sort at abc_flop_q
2019-04-17 Eddie HungRemove init* from xaiger, also topo-sort cells for...
2019-04-17 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-04-17 Eddie HungOptimise
2019-04-16 Eddie HungCIs before PIs; also sort each cell's connections befor...
2019-04-16 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-04-16 Eddie HungPort from xc7mux branch
2019-04-16 Eddie HungFix wire numbering
2019-04-16 Eddie HungDo not put constants into output_bits
2019-04-16 Eddie HungRemove write_verilog call
2019-04-16 Eddie HungFix spacing
2019-04-16 Eddie HungMerge branch 'xaig' into xc7mux
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