Merge pull request #897 from trcwm/libertyfixes
[yosys.git] / backends /
2019-03-23 Clifford WolfMerge pull request #893 from YosysHQ/clifford/btormeminit
2019-03-23 Clifford WolfAdd support for memory initialization to write_btor
2019-03-23 Clifford WolfFix BTOR output tags syntax in writye_btor
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-03-14 Clifford WolfMerge pull request #875 from YosysHQ/clifford/mutate
2019-03-14 Clifford WolfFix smtbmc.py handling of zero appended steps
2019-03-14 Clifford WolfMerge pull request #872 from YosysHQ/clifford/pmuxfix
2019-03-14 Clifford WolfFix a syntax bug in ilang backend related to process...
2019-03-14 Clifford WolfMerge pull request #869 from cr1901/win-shell
2019-03-13 William D. JonesInstall launcher executable when running yosys-smtbmc...
2019-03-13 Clifford WolfMerge pull request #868 from YosysHQ/clifford/fixmem
2019-03-12 Clifford WolfMerge pull request #866 from YosysHQ/clifford/idstuff
2019-03-11 Clifford WolfImprove determinism of IdString DB for similar scripts
2019-03-09 Clifford WolfMerge pull request #859 from smunaut/ice40_braminit
2019-03-09 Clifford WolfFix signed $shift/$shiftx handling in write_smt2
2019-03-09 Clifford WolfMerge pull request #858 from YosysHQ/clifford/svalabels
2019-03-07 Clifford WolfUse SVA label in smt export if available
2019-03-05 Clifford WolfMerge pull request #842 from litghost/merge_upstream
2019-03-05 Clifford WolfMerge pull request #850 from daveshah1/ecp5_warn_conflict
2019-03-05 Clifford WolfMerge pull request #851 from kprasadvnsi/master
2019-03-05 Clifford WolfMerge pull request #852 from ucb-bar/firrtlfixes
2019-03-04 Jim LawsonEnsure fid() calls make_id() for consistency; tests...
2019-03-01 Clifford WolfFix "write_edif -gndvccy"
2019-03-01 Clifford WolfMerge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
2019-02-28 Clifford WolfMerge pull request #834 from YosysHQ/clifford/siminit
2019-02-28 Clifford WolfAdd "write_verilog -siminit"
2019-02-28 Larry DoolittleReduce amount of trailing whitespace in code base
2019-02-28 Clifford WolfMerge pull request #794 from daveshah1/ecp5improve
2019-02-28 Clifford WolfMerge pull request #827 from ucb-bar/firrtlfixes
2019-02-28 Clifford WolfMerge pull request #833 from YosysHQ/clifford/fix831
2019-02-28 Clifford WolfFix smt2 code generation for partially initialized...
2019-02-26 Jim LawsonFix FIRRTL to Verilog process instance subfield assignment.
2019-02-24 Clifford WolfMerge pull request #812 from ucb-bar/arrayhierarchyfixes
2019-02-22 Clifford WolfMerge pull request #740 from daveshah1/improve_dress
2019-02-21 Clifford WolfMerge pull request #786 from YosysHQ/pmgen
2019-02-19 Eddie HungMerge pull request #805 from eddiehung/dff_init
2019-02-18 Eddie HungMerge branch 'dff_init' into read_aiger
2019-02-17 Eddie HungInstead of INIT param on cells, use initial statement...
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into dff_init
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-02-17 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-02-17 Clifford WolfMerge pull request #811 from ucb-bar/firrtlfixes
2019-02-15 Jim LawsonRemoved unused variables, functions.
2019-02-15 Jim LawsonUpdate cells supported for verilog to FIRRTL conversion.
2019-02-12 Clifford WolfMerge pull request #802 from whitequark/write_verilog_a...
2019-02-08 Eddie HungMerge remote-tracking branch 'origin/dff_init' into...
2019-02-06 Eddie HungRemove check for cell->name[0] == '$'
2019-02-06 Eddie HungMerge branch 'dff_init' of https://github.com/eddiehung...
2019-02-06 Eddie HungRefactor
2019-02-06 Eddie Hungwrite_verilog to cope with init attr on q when -noexpr
2019-02-06 Clifford WolfAdd missing blackslash-to-slash convertion to smtio...
2019-01-29 whitequarkwrite_verilog: correctly emit asynchronous transparent...
2019-01-27 Clifford WolfMerge pull request #798 from mmicko/master
2019-01-27 Clifford WolfMerge pull request #800 from whitequark/write_verilog_t...
2019-01-27 Clifford WolfMerge branch 'whitequark-write_verilog_keyword'
2019-01-27 whitequarkwrite_verilog: write $tribuf cell as ternary.
2019-01-27 whitequarkwrite_verilog: escape names that match SystemVerilog...
2019-01-17 Clifford WolfAdd "write_edif -gndvccy"
2019-01-15 Clifford WolfFix handling of $shiftx in Verilog back-end
2019-01-02 Clifford WolfMerge pull request #770 from whitequark/opt_expr_cmp
2019-01-02 Clifford WolfMerge pull request #755 from Icenowy/anlogic-dram-init
2019-01-02 Clifford WolfMerge pull request #750 from Icenowy/anlogic-ff-init
2019-01-02 Clifford WolfMerge pull request #773 from whitequark/opt_lut_elim_fixes
2019-01-02 Clifford WolfMerge pull request #772 from whitequark/synth_lut
2019-01-02 Clifford WolfMerge pull request #771 from whitequark/techmap_cmp2lut
2019-01-02 Clifford WolfMerge pull request #769 from whitequark/typos
2019-01-02 whitequarkFix typographical and grammatical errors and inconsiste...
2018-12-31 Clifford WolfMerge pull request #766 from Icenowy/anlogic-latches
2018-12-29 Larry DoolittleSquelch a little more trailing whitespace
2018-12-23 Clifford WolfMerge pull request #761 from whitequark/proc_clean_partial
2018-12-23 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys
2018-12-22 Clifford WolfMerge pull request #757 from whitequark/manual_mem
2018-12-19 Clifford WolfMerge pull request #752 from Icenowy/anlogic-lut-cost
2018-12-19 Clifford WolfMerge pull request #753 from Icenowy/anlogic-makefile-fix
2018-12-19 Clifford WolfMerge pull request #749 from Icenowy/anlogic-dram-fix
2018-12-18 Clifford WolfMinor style fixes
2018-12-18 Clifford WolfMerge pull request #748 from makaimann/add-btor-ops
2018-12-17 makaimannAdd btor ops for $mul, $div, $mod and $concat
2018-12-17 Clifford WolfMerge pull request #746 from Icenowy/anlogic-dram
2018-12-17 Clifford WolfMerge pull request #742 from whitequark/changelog
2018-12-17 Clifford WolfMerge pull request #741 from whitequark/ilang_slice_sigspec
2018-12-17 Clifford WolfMerge pull request #744 from whitequark/write_verilog_...
2018-12-16 whitequarkwrite_verilog: handle the $shift cell.
2018-12-16 Clifford WolfMerge pull request #736 from whitequark/select_assert_list
2018-12-16 Clifford WolfMerge pull request #704 from webhat/feature/fix-awk
2018-12-16 whitequarkwrite_verilog: add a missing newline.
2018-12-16 Clifford WolfMerge pull request #738 from smunaut/issue_737
2018-12-16 Clifford WolfMerge pull request #735 from daveshah1/trifixes
2018-12-16 Clifford WolfMerge pull request #724 from whitequark/equiv_opt
2018-12-16 Clifford WolfMerge pull request #734 from grahamedgecombe/fix-shuffl...
2018-12-16 Clifford WolfMerge pull request #730 from smunaut/ffssr_dont_touch
2018-12-16 Clifford WolfMerge pull request #729 from whitequark/write_verilog_i...
2018-12-16 Clifford WolfMerge pull request #725 from olofk/ram4k-init
2018-12-16 Clifford WolfMerge pull request #714 from daveshah1/abc_preserve_naming
2018-12-16 Clifford WolfMerge pull request #723 from whitequark/synth_ice40_map...
2018-12-16 Clifford WolfMerge pull request #722 from whitequark/rename_src
2018-12-16 Clifford WolfMerge pull request #720 from whitequark/master
2018-12-10 Clifford WolfAdd yosys-smtbmc support for btor witness
2018-12-08 Clifford WolfAdd "yosys-smtbmc --btorwit" skeleton
2018-12-08 Clifford WolfFix btor init value handling
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