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Fix handling of partial init attributes in write_verilog, fixes #997
[yosys.git] / backends /
2019-05-07 Clifford WolfFix handling of partial init attributes in write_verilo... tree | commitdiff
2019-05-06 Clifford WolfMerge pull request #946 from YosysHQ/clifford/specify tree | commitdiff
2019-05-06 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into... tree | commitdiff
2019-05-06 Clifford WolfAdd "real" keyword to ilang format tree | commitdiff
2019-05-06 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into... tree | commitdiff
2019-05-04 Clifford WolfImprove write_verilog specify support tree | commitdiff
2019-05-03 Eddie HungMerge remote-tracking branch 'origin/master' into cliff... tree | commitdiff
2019-05-03 Clifford WolfMerge pull request #969 from YosysHQ/clifford/pmgenstuff tree | commitdiff
2019-05-03 Clifford WolfMerge pull request #976 from YosysHQ/clifford/fix974 tree | commitdiff
2019-05-02 Clifford WolfMerge pull request #963 from YosysHQ/eddie/synth_xilinx... tree | commitdiff
2019-05-02 Eddie HungMerge pull request #978 from ucb-bar/fmtfirrtl tree | commitdiff
2019-05-02 Eddie HungMerge remote-tracking branch 'origin/master' into eddie... tree | commitdiff
2019-05-01 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys tree | commitdiff
2019-05-01 Jim LawsonRe-indent firrtl.cc:struct memory - no functional change. tree | commitdiff
2019-05-01 Clifford WolfMerge pull request #977 from ucb-bar/fixfirrtlmem tree | commitdiff
2019-05-01 Jim LawsonFix #938 - Crash occurs in case when use write_firrtl... tree | commitdiff
2019-04-30 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ... tree | commitdiff
2019-04-23 Clifford WolfRename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better... tree | commitdiff
2019-04-23 Clifford WolfAdd $specify2/$specify3 support to write_verilog tree | commitdiff
2019-04-23 Clifford WolfAdd support for $assert/$assume/$cover to write_verilog tree | commitdiff
2019-04-22 Eddie HungMerge pull request #914 from YosysHQ/xc7srl tree | commitdiff
2019-04-22 Clifford WolfMerge pull request #952 from YosysHQ/clifford/fix370 tree | commitdiff
2019-04-22 Clifford WolfMerge pull request #951 from YosysHQ/clifford/logdebug tree | commitdiff
2019-04-22 Clifford WolfMerge pull request #949 from YosysHQ/clifford/pmux2shim... tree | commitdiff
2019-04-22 Clifford WolfMerge pull request #953 from YosysHQ/clifford/fix948 tree | commitdiff
2019-04-22 Clifford WolfAdd support for zero-width signals to Verilog back... tree | commitdiff
2019-04-22 Clifford WolfMerge pull request #905 from christian-krieg/feature... tree | commitdiff
2019-04-22 Clifford WolfMerge pull request #941 from Wren6991/sim_lib_io_clke tree | commitdiff
2019-04-22 Clifford WolfMerge branch 'master' of https://github.com/dh73/yosys_... tree | commitdiff
2019-04-22 Clifford WolfMerge pull request #911 from mmicko/gowin-nobram tree | commitdiff
2019-04-22 Clifford WolfMerge pull request #909 from zachjs/master tree | commitdiff
2019-04-22 Clifford WolfMerge pull request #944 from YosysHQ/clifford/pmux2shiftx tree | commitdiff
2019-04-21 Eddie HungMerge branch 'master' into map_cells_before_map_luts tree | commitdiff
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/clifford/pmux2shif... tree | commitdiff
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl tree | commitdiff
2019-04-20 Clifford WolfMerge pull request #943 from YosysHQ/clifford/whitebox tree | commitdiff
2019-04-20 Eddie HungMerge remote-tracking branch 'origin/pmux2shiftx' into... tree | commitdiff
2019-04-20 Eddie HungMerge remote-tracking branch 'origin' into xc7srl tree | commitdiff
2019-04-20 Clifford WolfMerge pull request #942 from YosysHQ/clifford/fix931 tree | commitdiff
2019-04-19 Clifford WolfChange "ne" to "neq" in btor2 output tree | commitdiff
2019-04-19 Eddie HungRevert "write_json to not write contents (cells/wires... tree | commitdiff
2019-04-18 Eddie Hungwrite_json to not write contents (cells/wires) of white... tree | commitdiff
2019-04-18 Clifford WolfAdd "whitebox" attribute, add "read_verilog -wb" tree | commitdiff
2019-04-03 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl tree | commitdiff
2019-04-03 Clifford WolfMerge pull request #912 from YosysHQ/bram_addr_en tree | commitdiff
2019-04-03 Clifford WolfMerge pull request #910 from ucb-bar/memupdates tree | commitdiff
2019-04-01 Jim LawsonRefine memory support to deal with general Verilog... tree | commitdiff
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu... tree | commitdiff
2019-03-25 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl tree | commitdiff
2019-03-23 Clifford WolfMerge pull request #893 from YosysHQ/clifford/btormeminit tree | commitdiff
2019-03-23 Clifford WolfAdd support for memory initialization to write_btor tree | commitdiff
2019-03-23 Clifford WolfFix BTOR output tags syntax in writye_btor tree | commitdiff
2019-03-19 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl tree | commitdiff
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger tree | commitdiff
2019-03-14 Clifford WolfMerge pull request #875 from YosysHQ/clifford/mutate tree | commitdiff
2019-03-14 Clifford WolfFix smtbmc.py handling of zero appended steps tree | commitdiff
2019-03-14 Clifford WolfMerge pull request #872 from YosysHQ/clifford/pmuxfix tree | commitdiff
2019-03-14 Clifford WolfFix a syntax bug in ilang backend related to process... tree | commitdiff
2019-03-14 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl tree | commitdiff
2019-03-14 Clifford WolfMerge pull request #869 from cr1901/win-shell tree | commitdiff
2019-03-13 William D. JonesInstall launcher executable when running yosys-smtbmc... tree | commitdiff
2019-03-13 Clifford WolfMerge pull request #868 from YosysHQ/clifford/fixmem tree | commitdiff
2019-03-12 Clifford WolfMerge pull request #866 from YosysHQ/clifford/idstuff tree | commitdiff
2019-03-11 Clifford WolfImprove determinism of IdString DB for similar scripts tree | commitdiff
2019-03-09 Clifford WolfMerge pull request #859 from smunaut/ice40_braminit tree | commitdiff
2019-03-09 Clifford WolfFix signed $shift/$shiftx handling in write_smt2 tree | commitdiff
2019-03-09 Clifford WolfMerge pull request #858 from YosysHQ/clifford/svalabels tree | commitdiff
2019-03-07 Clifford WolfUse SVA label in smt export if available tree | commitdiff
2019-03-05 Clifford WolfMerge pull request #842 from litghost/merge_upstream tree | commitdiff
2019-03-05 Clifford WolfMerge pull request #850 from daveshah1/ecp5_warn_conflict tree | commitdiff
2019-03-05 Clifford WolfMerge pull request #851 from kprasadvnsi/master tree | commitdiff
2019-03-05 Clifford WolfMerge pull request #852 from ucb-bar/firrtlfixes tree | commitdiff
2019-03-04 Jim LawsonEnsure fid() calls make_id() for consistency; tests... tree | commitdiff
2019-03-01 Clifford WolfFix "write_edif -gndvccy" tree | commitdiff
2019-03-01 Clifford WolfMerge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode tree | commitdiff
2019-02-28 Clifford WolfMerge pull request #834 from YosysHQ/clifford/siminit tree | commitdiff
2019-02-28 Clifford WolfAdd "write_verilog -siminit" tree | commitdiff
2019-02-28 Larry DoolittleReduce amount of trailing whitespace in code base tree | commitdiff
2019-02-28 Clifford WolfMerge pull request #794 from daveshah1/ecp5improve tree | commitdiff
2019-02-28 Clifford WolfMerge pull request #827 from ucb-bar/firrtlfixes tree | commitdiff
2019-02-28 Clifford WolfMerge pull request #833 from YosysHQ/clifford/fix831 tree | commitdiff
2019-02-28 Clifford WolfFix smt2 code generation for partially initialized... tree | commitdiff
2019-02-26 Jim LawsonFix FIRRTL to Verilog process instance subfield assignment. tree | commitdiff
2019-02-24 Clifford WolfMerge pull request #812 from ucb-bar/arrayhierarchyfixes tree | commitdiff
2019-02-22 Clifford WolfMerge pull request #740 from daveshah1/improve_dress tree | commitdiff
2019-02-21 Clifford WolfMerge pull request #786 from YosysHQ/pmgen tree | commitdiff
2019-02-19 Eddie HungMerge pull request #805 from eddiehung/dff_init tree | commitdiff
2019-02-18 Eddie HungMerge branch 'dff_init' into read_aiger tree | commitdiff
2019-02-17 Eddie HungInstead of INIT param on cells, use initial statement... tree | commitdiff
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into dff_init tree | commitdiff
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger tree | commitdiff
2019-02-17 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into... tree | commitdiff
2019-02-17 Clifford WolfMerge pull request #811 from ucb-bar/firrtlfixes tree | commitdiff
2019-02-15 Jim LawsonRemoved unused variables, functions. tree | commitdiff
2019-02-15 Jim LawsonUpdate cells supported for verilog to FIRRTL conversion. tree | commitdiff
2019-02-12 Clifford WolfMerge pull request #802 from whitequark/write_verilog_a... tree | commitdiff
2019-02-08 Eddie HungMerge remote-tracking branch 'origin/dff_init' into... tree | commitdiff
2019-02-06 Eddie HungRemove check for cell->name[0] == '$' tree | commitdiff
2019-02-06 Eddie HungMerge branch 'dff_init' of https://github.com/eddiehung... tree | commitdiff
2019-02-06 Eddie HungRefactor tree | commitdiff
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