2015-01-01 |
Clifford Wolf | Fixed memory->start_offset handling |
tree | commitdiff |
2014-12-26 |
Clifford Wolf | Replaced std::unordered_map as implementation for Yosys... |
tree | commitdiff |
2014-12-26 |
Clifford Wolf | Added Yosys::{dict,nodict,vector} container types |
tree | commitdiff |
2014-12-25 |
Clifford Wolf | Various fixes and improvements in "write_smt2 -bv" |
tree | commitdiff |
2014-12-25 |
Clifford Wolf | Various fixes and improvements in write_smt2 |
tree | commitdiff |
2014-12-25 |
Clifford Wolf | Added support for most BV cell types to write_smt2 |
tree | commitdiff |
2014-12-25 |
Clifford Wolf | Added "write_smt2 -bv" and other write_smt2 improvements |
tree | commitdiff |
2014-12-24 |
Clifford Wolf | Added write_smt2 (only gate level logic supported so... |
tree | commitdiff |
2014-12-24 |
Clifford Wolf | Renamed extend() to extend_xx(), changed most users... |
tree | commitdiff |
2014-12-19 |
Clifford Wolf | Added $dffe support to write_verilog |
tree | commitdiff |
2014-12-19 |
Clifford Wolf | Fixed another bug in write_blif handling of $lut cells |
tree | commitdiff |
2014-12-17 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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2014-12-17 |
Clifford Wolf | Fixed writing of $lut cells in BLIF backend |
tree | commitdiff |
2014-12-14 |
Clifford Wolf | Added "write_blif -undef" and support for special ... |
tree | commitdiff |
2014-12-14 |
Clifford Wolf | Added "write_blif -blackbox" |
tree | commitdiff |
2014-12-14 |
Clifford Wolf | Added "blif -unbuf" feature |
tree | commitdiff |
2014-11-09 |
Clifford Wolf | Added log_warning() API |
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2014-11-07 |
Clifford Wolf | Fixed generation of temp names in verilog backend |
tree | commitdiff |
2014-10-10 |
Clifford Wolf | Renamed SIZE() to GetSize() because of name collision... |
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2014-09-27 |
Clifford Wolf | namespace Yosys |
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2014-09-22 |
Clifford Wolf | Merge pull request #39 from ahmedirfan1983/master |
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2014-09-22 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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2014-09-19 |
Clifford Wolf | Sorting of object names in ilang backend |
tree | commitdiff |
2014-09-18 |
ahmedirfan1983 | fixed memory next issue, when same memory is written... |
tree | commitdiff |
2014-09-06 |
Clifford Wolf | Various bug fixes (related to $macc model testing) |
tree | commitdiff |
2014-09-06 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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2014-09-06 |
Clifford Wolf | Merge pull request #38 from rubund/master |
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2014-09-06 |
Ruben Undheim | Corrected spelling mistakes found by lintian |
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2014-09-04 |
Clifford Wolf | Removed $bu0 cell type |
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2014-09-03 |
Clifford Wolf | Using $pos models for $bu0 |
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2014-09-02 |
Ahmed Irfan | added $pmux cell translation |
tree | commitdiff |
2014-09-01 |
Clifford Wolf | Using std::vector<RTLIL::State> instead of RTLIL::Const... |
tree | commitdiff |
2014-08-23 |
Clifford Wolf | Changed frontend-api from FILE to std::istream |
tree | commitdiff |
2014-08-23 |
Clifford Wolf | Changed backend-api from FILE to std::ostream |
tree | commitdiff |
2014-08-16 |
Clifford Wolf | Fixed AOI/OAI expr handling in verilog backend |
tree | commitdiff |
2014-08-16 |
Clifford Wolf | Added additional gate types: $_NAND_ $_NOR_ $_XNOR_... |
tree | commitdiff |
2014-08-15 |
Clifford Wolf | Renamed $lut ports to follow A-Y naming scheme |
tree | commitdiff |
2014-08-15 |
Clifford Wolf | Renamed $_INV_ cell type to $_NOT_ |
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2014-08-14 |
Clifford Wolf | Refactoring of CellType class |
tree | commitdiff |
2014-08-02 |
Clifford Wolf | Be more conservative with printing decimal numbers... |
tree | commitdiff |
2014-08-02 |
Clifford Wolf | Improved verilog output for ordinary $mux cells |
tree | commitdiff |
2014-08-02 |
Clifford Wolf | No implicit conversion from IdString to anything else |
tree | commitdiff |
2014-08-02 |
Clifford Wolf | More cleanups related to RTLIL::IdString usage |
tree | commitdiff |
2014-07-31 |
Clifford Wolf | Renamed port access function on RTLIL::Cell, added... |
tree | commitdiff |
2014-07-31 |
Clifford Wolf | Moved some stuff to kernel/yosys.{h,cc}, using Yosys... |
tree | commitdiff |
2014-07-29 |
Clifford Wolf | Renamed "write_autotest" to "test_autotb" and moved... |
tree | commitdiff |
2014-07-29 |
Clifford Wolf | Added $shift and $shiftx cell types (needed for correct... |
tree | commitdiff |
2014-07-28 |
Clifford Wolf | Added support for "upto" wires to Verilog front- and... |
tree | commitdiff |
2014-07-28 |
Clifford Wolf | Added wire->upto flag for signals such as "wire [0... |
tree | commitdiff |
2014-07-28 |
Clifford Wolf | Using log_assert() instead of assert() |
tree | commitdiff |
2014-07-27 |
Clifford Wolf | Refactoring: Renamed RTLIL::Design::modules to modules_ |
tree | commitdiff |
2014-07-26 |
Clifford Wolf | Refactoring: Renamed RTLIL::Module::cells to cells_ |
tree | commitdiff |
2014-07-26 |
Clifford Wolf | Refactoring: Renamed RTLIL::Module::wires to wires_ |
tree | commitdiff |
2014-07-26 |
Clifford Wolf | More RTLIL::Cell API usage cleanups |
tree | commitdiff |
2014-07-26 |
Clifford Wolf | Added RTLIL::Cell::has(portname) |
tree | commitdiff |
2014-07-26 |
Clifford Wolf | Merge automatic and manual code changes for new cell... |
tree | commitdiff |
2014-07-26 |
Clifford Wolf | Manual fixes for new cell connections API |
tree | commitdiff |
2014-07-26 |
Clifford Wolf | Changed users of cell->connections_ to the new API... |
tree | commitdiff |
2014-07-26 |
Clifford Wolf | Renamed RTLIL::{Module,Cell}::connections to connections_ |
tree | commitdiff |
2014-07-25 |
Clifford Wolf | Various RTLIL::SigSpec related code cleanups |
tree | commitdiff |
2014-07-24 |
Clifford Wolf | Replaced more old SigChunk programming patterns |
tree | commitdiff |
2014-07-23 |
Clifford Wolf | Removed RTLIL::SigSpec::optimize() |
tree | commitdiff |
2014-07-23 |
Clifford Wolf | Removed RTLIL::SigSpec::expand() method |
tree | commitdiff |
2014-07-23 |
Clifford Wolf | Merge branch: Refactoring {SigSpec|SigChunk}(RTLIL... |
tree | commitdiff |
2014-07-23 |
Clifford Wolf | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ... |
tree | commitdiff |
2014-07-23 |
Clifford Wolf | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ... |
tree | commitdiff |
2014-07-22 |
Clifford Wolf | SigSpec refactoring: change RTLIL::SigSpec::chunks... |
tree | commitdiff |
2014-07-22 |
Clifford Wolf | SigSpec refactoring: using the accessor functions every... |
tree | commitdiff |
2014-07-22 |
Clifford Wolf | SigSpec refactoring: renamed chunks and width to __chun... |
tree | commitdiff |
2014-07-21 |
Clifford Wolf | Added "autoidx" statement to ilang file format |
tree | commitdiff |
2014-07-20 |
Clifford Wolf | Use functions instead of always blocks for $mux/$pmux... |
tree | commitdiff |
2014-07-19 |
Clifford Wolf | Added support for $bu0 to verilog backend |
tree | commitdiff |
2014-03-13 |
Clifford Wolf | Merge branch 'master' of https://github.com/Siesh1oo... |
tree | commitdiff |
2014-03-13 |
Clifford Wolf | Merged OSX fixes from Siesh1oo with some modifications |
tree | commitdiff |
2014-03-07 |
Clifford Wolf | Use log_abort() and log_assert() in BTOR backend |
tree | commitdiff |
2014-02-22 |
Clifford Wolf | Added $lut support to blif backend (by user eddiehung... |
tree | commitdiff |
2014-02-21 |
Clifford Wolf | Better handling of nameDef and nameRef in edif backend |
tree | commitdiff |
2014-02-21 |
Clifford Wolf | Fixed instantiating multi-bit ports in edif backend |
tree | commitdiff |
2014-02-21 |
Clifford Wolf | Renamed "write_blif -subckt" to "write_blif -icells... |
tree | commitdiff |
2014-02-13 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
tree | commitdiff |
2014-02-12 |
Clifford Wolf | Merge pull request #26 from ahmedirfan1983/btor |
tree | commitdiff |
2014-02-12 |
Ahmed Irfan | modified btor synthesis script for correct use of splic... |
tree | commitdiff |
2014-02-11 |
Ahmed Irfan | disabling splice command in the script |
tree | commitdiff |
2014-02-11 |
Ahmed Irfan | register output corrected |
tree | commitdiff |
2014-02-11 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
tree | commitdiff |
2014-02-11 |
Ahmed Irfan | added concat and slice cell translation |
tree | commitdiff |
2014-02-07 |
Clifford Wolf | Added $slice and $concat cell types |
tree | commitdiff |
2014-02-06 |
Clifford Wolf | Fixed gcc compiler warnings with release build |
tree | commitdiff |
2014-02-05 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
tree | commitdiff |
2014-02-05 |
Clifford Wolf | Added BTOR backend README file |
tree | commitdiff |
2014-02-04 |
Clifford Wolf | Added support for dump -append |
tree | commitdiff |
2014-02-03 |
Clifford Wolf | Added TRANSPARENT parameter to $memrd (and RD_TRANSPARE... |
tree | commitdiff |
2014-01-26 |
Clifford Wolf | Merge branch 'btor' of https://github.com/ahmedirfan198... |
tree | commitdiff |
2014-01-26 |
Clifford Wolf | Merge pull request #21 from hansiglaser/master |
tree | commitdiff |
2014-01-25 |
Johann Glaser | beautified write_intersynth |
tree | commitdiff |
2014-01-25 |
Ahmed Irfan | root bug corrected |
tree | commitdiff |
2014-01-24 |
Clifford Wolf | Merge branch 'btor' |
tree | commitdiff |
2014-01-24 |
Ahmed Irfan | removed regex include |
tree | commitdiff |
2014-01-24 |
Ahmed Irfan | merged clifford changes + removed regex |
tree | commitdiff |
2014-01-24 |
Clifford Wolf | Use techmap -share_map in btor scripts |
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next |