Various improvements in ModIndex
[yosys.git] / backends /
2014-12-26 Clifford WolfReplaced std::unordered_map as implementation for Yosys...
2014-12-26 Clifford WolfAdded Yosys::{dict,nodict,vector} container types
2014-12-25 Clifford WolfVarious fixes and improvements in "write_smt2 -bv"
2014-12-25 Clifford WolfVarious fixes and improvements in write_smt2
2014-12-25 Clifford WolfAdded support for most BV cell types to write_smt2
2014-12-25 Clifford WolfAdded "write_smt2 -bv" and other write_smt2 improvements
2014-12-24 Clifford WolfAdded write_smt2 (only gate level logic supported so...
2014-12-24 Clifford WolfRenamed extend() to extend_xx(), changed most users...
2014-12-19 Clifford WolfAdded $dffe support to write_verilog
2014-12-19 Clifford WolfFixed another bug in write_blif handling of $lut cells
2014-12-17 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-12-17 Clifford WolfFixed writing of $lut cells in BLIF backend
2014-12-14 Clifford WolfAdded "write_blif -undef" and support for special ...
2014-12-14 Clifford WolfAdded "write_blif -blackbox"
2014-12-14 Clifford WolfAdded "blif -unbuf" feature
2014-11-09 Clifford WolfAdded log_warning() API
2014-11-07 Clifford WolfFixed generation of temp names in verilog backend
2014-10-10 Clifford WolfRenamed SIZE() to GetSize() because of name collision...
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Clifford WolfMerge pull request #39 from ahmedirfan1983/master
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-09-19 Clifford WolfSorting of object names in ilang backend
2014-09-18 ahmedirfan1983fixed memory next issue, when same memory is written...
2014-09-06 Clifford WolfVarious bug fixes (related to $macc model testing)
2014-09-06 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-09-06 Clifford WolfMerge pull request #38 from rubund/master
2014-09-06 Ruben UndheimCorrected spelling mistakes found by lintian
2014-09-04 Clifford WolfRemoved $bu0 cell type
2014-09-03 Clifford WolfUsing $pos models for $bu0
2014-09-02 Ahmed Irfanadded $pmux cell translation
2014-09-01 Clifford WolfUsing std::vector<RTLIL::State> instead of RTLIL::Const...
2014-08-23 Clifford WolfChanged frontend-api from FILE to std::istream
2014-08-23 Clifford WolfChanged backend-api from FILE to std::ostream
2014-08-16 Clifford WolfFixed AOI/OAI expr handling in verilog backend
2014-08-16 Clifford WolfAdded additional gate types: $_NAND_ $_NOR_ $_XNOR_...
2014-08-15 Clifford WolfRenamed $lut ports to follow A-Y naming scheme
2014-08-15 Clifford WolfRenamed $_INV_ cell type to $_NOT_
2014-08-14 Clifford WolfRefactoring of CellType class
2014-08-02 Clifford WolfBe more conservative with printing decimal numbers...
2014-08-02 Clifford WolfImproved verilog output for ordinary $mux cells
2014-08-02 Clifford WolfNo implicit conversion from IdString to anything else
2014-08-02 Clifford WolfMore cleanups related to RTLIL::IdString usage
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added...
2014-07-31 Clifford WolfMoved some stuff to kernel/yosys.{h,cc}, using Yosys...
2014-07-29 Clifford WolfRenamed "write_autotest" to "test_autotb" and moved...
2014-07-29 Clifford WolfAdded $shift and $shiftx cell types (needed for correct...
2014-07-28 Clifford WolfAdded support for "upto" wires to Verilog front- and...
2014-07-28 Clifford WolfAdded wire->upto flag for signals such as "wire [0...
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_
2014-07-26 Clifford WolfMore RTLIL::Cell API usage cleanups
2014-07-26 Clifford WolfAdded RTLIL::Cell::has(portname)
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfManual fixes for new cell connections API
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_
2014-07-25 Clifford WolfVarious RTLIL::SigSpec related code cleanups
2014-07-24 Clifford WolfReplaced more old SigChunk programming patterns
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::optimize()
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::expand() method
2014-07-23 Clifford WolfMerge branch: Refactoring {SigSpec|SigChunk}(RTLIL...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-22 Clifford WolfSigSpec refactoring: change RTLIL::SigSpec::chunks...
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every...
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun...
2014-07-21 Clifford WolfAdded "autoidx" statement to ilang file format
2014-07-20 Clifford WolfUse functions instead of always blocks for $mux/$pmux...
2014-07-19 Clifford WolfAdded support for $bu0 to verilog backend
2014-03-13 Clifford WolfMerge branch 'master' of https://github.com/Siesh1oo...
2014-03-13 Clifford WolfMerged OSX fixes from Siesh1oo with some modifications
2014-03-07 Clifford WolfUse log_abort() and log_assert() in BTOR backend
2014-02-22 Clifford WolfAdded $lut support to blif backend (by user eddiehung...
2014-02-21 Clifford WolfBetter handling of nameDef and nameRef in edif backend
2014-02-21 Clifford WolfFixed instantiating multi-bit ports in edif backend
2014-02-21 Clifford WolfRenamed "write_blif -subckt" to "write_blif -icells...
2014-02-13 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-02-12 Clifford WolfMerge pull request #26 from ahmedirfan1983/btor
2014-02-12 Ahmed Irfanmodified btor synthesis script for correct use of splic...
2014-02-11 Ahmed Irfandisabling splice command in the script
2014-02-11 Ahmed Irfanregister output corrected
2014-02-11 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-02-11 Ahmed Irfanadded concat and slice cell translation
2014-02-07 Clifford WolfAdded $slice and $concat cell types
2014-02-06 Clifford WolfFixed gcc compiler warnings with release build
2014-02-05 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-02-05 Clifford WolfAdded BTOR backend README file
2014-02-04 Clifford WolfAdded support for dump -append
2014-02-03 Clifford WolfAdded TRANSPARENT parameter to $memrd (and RD_TRANSPARE...
2014-01-26 Clifford WolfMerge branch 'btor' of https://github.com/ahmedirfan198...
2014-01-26 Clifford WolfMerge pull request #21 from hansiglaser/master
2014-01-25 Johann Glaserbeautified write_intersynth
2014-01-25 Ahmed Irfanroot bug corrected
2014-01-24 Clifford WolfMerge branch 'btor'
2014-01-24 Ahmed Irfanremoved regex include
2014-01-24 Ahmed Irfanmerged clifford changes + removed regex
2014-01-24 Clifford WolfUse techmap -share_map in btor scripts
2014-01-24 Clifford WolfMoved btor scripts to backends/btor/
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