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bugfix in blif front-end
[yosys.git] / backends /
2015-05-11 Clifford WolfMerge pull request #63 from wluker/verilog-backend-mem tree | commitdiff
2015-05-11 luke whittleseyFixed bug in $mem cell verilog code generation. tree | commitdiff
2015-05-10 Clifford WolfDisabled broken $mem support in verilog backend tree | commitdiff
2015-05-10 Clifford WolfMerge pull request #62 from wluker/verilog-backend-mem tree | commitdiff
2015-05-10 luke whittleseyMade changes recommended by Clifford Wolf ... tree | commitdiff
2015-05-08 luke whittleseyVerilog backend for $mem cells should now be able to... tree | commitdiff
2015-05-07 luke whittleseyAdded support for $mem cells in the verilog backend. tree | commitdiff
2015-04-09 Clifford WolfMinor fixes in handling of "init" attribute tree | commitdiff
2015-04-08 Clifford WolfRemoved "techmap -share_map" (use "-map +/filename... tree | commitdiff
2015-04-05 Clifford WolfAdded "port_directions" to write_json output tree | commitdiff
2015-04-04 Clifford WolfAdded "init" attribute support to verilog backend tree | commitdiff
2015-04-04 Clifford WolfMerge pull request #55 from ahmedirfan1983/master tree | commitdiff
2015-04-03 Ahmed IrfanUpdate README tree | commitdiff
2015-04-03 Ahmed IrfanDelete btor.ys tree | commitdiff
2015-04-03 Ahmed IrfanUpdate README tree | commitdiff
2015-04-03 Ahmed Irfanseparated memory next from write cell tree | commitdiff
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... tree | commitdiff
2015-03-18 Clifford WolfAdded Verilog backend $dffsr support tree | commitdiff
2015-03-06 Clifford WolfDocumentation for JSON format, added attributes tree | commitdiff
2015-03-03 Clifford WolfJson bugfix tree | commitdiff
2015-03-03 Clifford WolfJson backend improvements tree | commitdiff
2015-03-02 Clifford WolfAdded write_blif -attr tree | commitdiff
2015-03-02 Clifford WolfAdded JSON backend tree | commitdiff
2015-02-26 Clifford WolfAdded $assume support to write_smt2 tree | commitdiff
2015-02-22 Clifford WolfMinor "write_smt2" help msg change tree | commitdiff
2015-02-22 Clifford WolfAdded "<mod>_a" and "<mod>_i" to write_smt2 output tree | commitdiff
2015-02-13 Clifford WolfFixed "write_verilog -attr2comment" handling of "*... tree | commitdiff
2015-02-01 Clifford WolfAdded EDIF backend support for multi-bit cell ports tree | commitdiff
2015-01-31 Clifford WolfShorter "dump" options tree | commitdiff
2015-01-24 Clifford WolfAdded ENABLE_NDEBUG makefile options tree | commitdiff
2015-01-23 Clifford WolfAdded dict/pool.sort() tree | commitdiff
2015-01-02 Clifford WolfCosmetic changes in verilog output format tree | commitdiff
2015-01-01 Clifford WolfFixed memory->start_offset handling tree | commitdiff
2014-12-26 Clifford WolfReplaced std::unordered_map as implementation for Yosys... tree | commitdiff
2014-12-26 Clifford WolfAdded Yosys::{dict,nodict,vector} container types tree | commitdiff
2014-12-25 Clifford WolfVarious fixes and improvements in "write_smt2 -bv" tree | commitdiff
2014-12-25 Clifford WolfVarious fixes and improvements in write_smt2 tree | commitdiff
2014-12-25 Clifford WolfAdded support for most BV cell types to write_smt2 tree | commitdiff
2014-12-25 Clifford WolfAdded "write_smt2 -bv" and other write_smt2 improvements tree | commitdiff
2014-12-24 Clifford WolfAdded write_smt2 (only gate level logic supported so... tree | commitdiff
2014-12-24 Clifford WolfRenamed extend() to extend_xx(), changed most users... tree | commitdiff
2014-12-19 Clifford WolfAdded $dffe support to write_verilog tree | commitdiff
2014-12-19 Clifford WolfFixed another bug in write_blif handling of $lut cells tree | commitdiff
2014-12-17 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2014-12-17 Clifford WolfFixed writing of $lut cells in BLIF backend tree | commitdiff
2014-12-14 Clifford WolfAdded "write_blif -undef" and support for special ... tree | commitdiff
2014-12-14 Clifford WolfAdded "write_blif -blackbox" tree | commitdiff
2014-12-14 Clifford WolfAdded "blif -unbuf" feature tree | commitdiff
2014-11-09 Clifford WolfAdded log_warning() API tree | commitdiff
2014-11-07 Clifford WolfFixed generation of temp names in verilog backend tree | commitdiff
2014-10-10 Clifford WolfRenamed SIZE() to GetSize() because of name collision... tree | commitdiff
2014-09-27 Clifford Wolfnamespace Yosys tree | commitdiff
2014-09-22 Clifford WolfMerge pull request #39 from ahmedirfan1983/master tree | commitdiff
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... tree | commitdiff
2014-09-19 Clifford WolfSorting of object names in ilang backend tree | commitdiff
2014-09-18 ahmedirfan1983fixed memory next issue, when same memory is written... tree | commitdiff
2014-09-06 Clifford WolfVarious bug fixes (related to $macc model testing) tree | commitdiff
2014-09-06 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2014-09-06 Clifford WolfMerge pull request #38 from rubund/master tree | commitdiff
2014-09-06 Ruben UndheimCorrected spelling mistakes found by lintian tree | commitdiff
2014-09-04 Clifford WolfRemoved $bu0 cell type tree | commitdiff
2014-09-03 Clifford WolfUsing $pos models for $bu0 tree | commitdiff
2014-09-02 Ahmed Irfanadded $pmux cell translation tree | commitdiff
2014-09-01 Clifford WolfUsing std::vector<RTLIL::State> instead of RTLIL::Const... tree | commitdiff
2014-08-23 Clifford WolfChanged frontend-api from FILE to std::istream tree | commitdiff
2014-08-23 Clifford WolfChanged backend-api from FILE to std::ostream tree | commitdiff
2014-08-16 Clifford WolfFixed AOI/OAI expr handling in verilog backend tree | commitdiff
2014-08-16 Clifford WolfAdded additional gate types: $_NAND_ $_NOR_ $_XNOR_... tree | commitdiff
2014-08-15 Clifford WolfRenamed $lut ports to follow A-Y naming scheme tree | commitdiff
2014-08-15 Clifford WolfRenamed $_INV_ cell type to $_NOT_ tree | commitdiff
2014-08-14 Clifford WolfRefactoring of CellType class tree | commitdiff
2014-08-02 Clifford WolfBe more conservative with printing decimal numbers... tree | commitdiff
2014-08-02 Clifford WolfImproved verilog output for ordinary $mux cells tree | commitdiff
2014-08-02 Clifford WolfNo implicit conversion from IdString to anything else tree | commitdiff
2014-08-02 Clifford WolfMore cleanups related to RTLIL::IdString usage tree | commitdiff
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added... tree | commitdiff
2014-07-31 Clifford WolfMoved some stuff to kernel/yosys.{h,cc}, using Yosys... tree | commitdiff
2014-07-29 Clifford WolfRenamed "write_autotest" to "test_autotb" and moved... tree | commitdiff
2014-07-29 Clifford WolfAdded $shift and $shiftx cell types (needed for correct... tree | commitdiff
2014-07-28 Clifford WolfAdded support for "upto" wires to Verilog front- and... tree | commitdiff
2014-07-28 Clifford WolfAdded wire->upto flag for signals such as "wire [0... tree | commitdiff
2014-07-28 Clifford WolfUsing log_assert() instead of assert() tree | commitdiff
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_ tree | commitdiff
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_ tree | commitdiff
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_ tree | commitdiff
2014-07-26 Clifford WolfMore RTLIL::Cell API usage cleanups tree | commitdiff
2014-07-26 Clifford WolfAdded RTLIL::Cell::has(portname) tree | commitdiff
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell... tree | commitdiff
2014-07-26 Clifford WolfManual fixes for new cell connections API tree | commitdiff
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API... tree | commitdiff
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_ tree | commitdiff
2014-07-25 Clifford WolfVarious RTLIL::SigSpec related code cleanups tree | commitdiff
2014-07-24 Clifford WolfReplaced more old SigChunk programming patterns tree | commitdiff
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::optimize() tree | commitdiff
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::expand() method tree | commitdiff
2014-07-23 Clifford WolfMerge branch: Refactoring {SigSpec|SigChunk}(RTLIL... tree | commitdiff
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ... tree | commitdiff
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ... tree | commitdiff
2014-07-22 Clifford WolfSigSpec refactoring: change RTLIL::SigSpec::chunks... tree | commitdiff
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every... tree | commitdiff
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