2015-05-11 |
Clifford Wolf | Merge pull request #63 from wluker/verilog-backend-mem |
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2015-05-11 |
luke whittlesey | Fixed bug in $mem cell verilog code generation. |
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2015-05-10 |
Clifford Wolf | Disabled broken $mem support in verilog backend |
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2015-05-10 |
Clifford Wolf | Merge pull request #62 from wluker/verilog-backend-mem |
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2015-05-10 |
luke whittlesey | Made changes recommended by Clifford Wolf ... |
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2015-05-08 |
luke whittlesey | Verilog backend for $mem cells should now be able to... |
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2015-05-07 |
luke whittlesey | Added support for $mem cells in the verilog backend. |
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2015-04-09 |
Clifford Wolf | Minor fixes in handling of "init" attribute |
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2015-04-08 |
Clifford Wolf | Removed "techmap -share_map" (use "-map +/filename... |
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2015-04-05 |
Clifford Wolf | Added "port_directions" to write_json output |
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2015-04-04 |
Clifford Wolf | Added "init" attribute support to verilog backend |
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2015-04-04 |
Clifford Wolf | Merge pull request #55 from ahmedirfan1983/master |
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2015-04-03 |
Ahmed Irfan | Update README |
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2015-04-03 |
Ahmed Irfan | Delete btor.ys |
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2015-04-03 |
Ahmed Irfan | Update README |
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2015-04-03 |
Ahmed Irfan | separated memory next from write cell |
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2015-04-03 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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2015-03-18 |
Clifford Wolf | Added Verilog backend $dffsr support |
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2015-03-06 |
Clifford Wolf | Documentation for JSON format, added attributes |
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2015-03-03 |
Clifford Wolf | Json bugfix |
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2015-03-03 |
Clifford Wolf | Json backend improvements |
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2015-03-02 |
Clifford Wolf | Added write_blif -attr |
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2015-03-02 |
Clifford Wolf | Added JSON backend |
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2015-02-26 |
Clifford Wolf | Added $assume support to write_smt2 |
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2015-02-22 |
Clifford Wolf | Minor "write_smt2" help msg change |
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2015-02-22 |
Clifford Wolf | Added "<mod>_a" and "<mod>_i" to write_smt2 output |
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2015-02-13 |
Clifford Wolf | Fixed "write_verilog -attr2comment" handling of "*... |
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2015-02-01 |
Clifford Wolf | Added EDIF backend support for multi-bit cell ports |
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2015-01-31 |
Clifford Wolf | Shorter "dump" options |
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2015-01-24 |
Clifford Wolf | Added ENABLE_NDEBUG makefile options |
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2015-01-23 |
Clifford Wolf | Added dict/pool.sort() |
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2015-01-02 |
Clifford Wolf | Cosmetic changes in verilog output format |
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2015-01-01 |
Clifford Wolf | Fixed memory->start_offset handling |
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2014-12-26 |
Clifford Wolf | Replaced std::unordered_map as implementation for Yosys... |
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2014-12-26 |
Clifford Wolf | Added Yosys::{dict,nodict,vector} container types |
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2014-12-25 |
Clifford Wolf | Various fixes and improvements in "write_smt2 -bv" |
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2014-12-25 |
Clifford Wolf | Various fixes and improvements in write_smt2 |
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2014-12-25 |
Clifford Wolf | Added support for most BV cell types to write_smt2 |
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2014-12-25 |
Clifford Wolf | Added "write_smt2 -bv" and other write_smt2 improvements |
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2014-12-24 |
Clifford Wolf | Added write_smt2 (only gate level logic supported so... |
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2014-12-24 |
Clifford Wolf | Renamed extend() to extend_xx(), changed most users... |
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2014-12-19 |
Clifford Wolf | Added $dffe support to write_verilog |
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2014-12-19 |
Clifford Wolf | Fixed another bug in write_blif handling of $lut cells |
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2014-12-17 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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2014-12-17 |
Clifford Wolf | Fixed writing of $lut cells in BLIF backend |
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2014-12-14 |
Clifford Wolf | Added "write_blif -undef" and support for special ... |
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2014-12-14 |
Clifford Wolf | Added "write_blif -blackbox" |
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2014-12-14 |
Clifford Wolf | Added "blif -unbuf" feature |
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2014-11-09 |
Clifford Wolf | Added log_warning() API |
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2014-11-07 |
Clifford Wolf | Fixed generation of temp names in verilog backend |
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2014-10-10 |
Clifford Wolf | Renamed SIZE() to GetSize() because of name collision... |
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2014-09-27 |
Clifford Wolf | namespace Yosys |
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2014-09-22 |
Clifford Wolf | Merge pull request #39 from ahmedirfan1983/master |
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2014-09-22 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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2014-09-19 |
Clifford Wolf | Sorting of object names in ilang backend |
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2014-09-18 |
ahmedirfan1983 | fixed memory next issue, when same memory is written... |
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2014-09-06 |
Clifford Wolf | Various bug fixes (related to $macc model testing) |
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2014-09-06 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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2014-09-06 |
Clifford Wolf | Merge pull request #38 from rubund/master |
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2014-09-06 |
Ruben Undheim | Corrected spelling mistakes found by lintian |
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2014-09-04 |
Clifford Wolf | Removed $bu0 cell type |
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2014-09-03 |
Clifford Wolf | Using $pos models for $bu0 |
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2014-09-02 |
Ahmed Irfan | added $pmux cell translation |
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2014-09-01 |
Clifford Wolf | Using std::vector<RTLIL::State> instead of RTLIL::Const... |
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2014-08-23 |
Clifford Wolf | Changed frontend-api from FILE to std::istream |
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2014-08-23 |
Clifford Wolf | Changed backend-api from FILE to std::ostream |
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2014-08-16 |
Clifford Wolf | Fixed AOI/OAI expr handling in verilog backend |
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2014-08-16 |
Clifford Wolf | Added additional gate types: $_NAND_ $_NOR_ $_XNOR_... |
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2014-08-15 |
Clifford Wolf | Renamed $lut ports to follow A-Y naming scheme |
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2014-08-15 |
Clifford Wolf | Renamed $_INV_ cell type to $_NOT_ |
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2014-08-14 |
Clifford Wolf | Refactoring of CellType class |
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2014-08-02 |
Clifford Wolf | Be more conservative with printing decimal numbers... |
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2014-08-02 |
Clifford Wolf | Improved verilog output for ordinary $mux cells |
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2014-08-02 |
Clifford Wolf | No implicit conversion from IdString to anything else |
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2014-08-02 |
Clifford Wolf | More cleanups related to RTLIL::IdString usage |
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2014-07-31 |
Clifford Wolf | Renamed port access function on RTLIL::Cell, added... |
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2014-07-31 |
Clifford Wolf | Moved some stuff to kernel/yosys.{h,cc}, using Yosys... |
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2014-07-29 |
Clifford Wolf | Renamed "write_autotest" to "test_autotb" and moved... |
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2014-07-29 |
Clifford Wolf | Added $shift and $shiftx cell types (needed for correct... |
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2014-07-28 |
Clifford Wolf | Added support for "upto" wires to Verilog front- and... |
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2014-07-28 |
Clifford Wolf | Added wire->upto flag for signals such as "wire [0... |
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2014-07-28 |
Clifford Wolf | Using log_assert() instead of assert() |
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2014-07-27 |
Clifford Wolf | Refactoring: Renamed RTLIL::Design::modules to modules_ |
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2014-07-26 |
Clifford Wolf | Refactoring: Renamed RTLIL::Module::cells to cells_ |
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2014-07-26 |
Clifford Wolf | Refactoring: Renamed RTLIL::Module::wires to wires_ |
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2014-07-26 |
Clifford Wolf | More RTLIL::Cell API usage cleanups |
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2014-07-26 |
Clifford Wolf | Added RTLIL::Cell::has(portname) |
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2014-07-26 |
Clifford Wolf | Merge automatic and manual code changes for new cell... |
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2014-07-26 |
Clifford Wolf | Manual fixes for new cell connections API |
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2014-07-26 |
Clifford Wolf | Changed users of cell->connections_ to the new API... |
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2014-07-26 |
Clifford Wolf | Renamed RTLIL::{Module,Cell}::connections to connections_ |
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2014-07-25 |
Clifford Wolf | Various RTLIL::SigSpec related code cleanups |
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2014-07-24 |
Clifford Wolf | Replaced more old SigChunk programming patterns |
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2014-07-23 |
Clifford Wolf | Removed RTLIL::SigSpec::optimize() |
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2014-07-23 |
Clifford Wolf | Removed RTLIL::SigSpec::expand() method |
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2014-07-23 |
Clifford Wolf | Merge branch: Refactoring {SigSpec|SigChunk}(RTLIL... |
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2014-07-23 |
Clifford Wolf | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ... |
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2014-07-23 |
Clifford Wolf | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ... |
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2014-07-22 |
Clifford Wolf | SigSpec refactoring: change RTLIL::SigSpec::chunks... |
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2014-07-22 |
Clifford Wolf | SigSpec refactoring: using the accessor functions every... |
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