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Fixed trailing whitespaces
[yosys.git]
/
backends
/
2015-07-02
Clifford Wolf
Fixed trailing whitespaces
tree
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commitdiff
2015-06-19
Clifford Wolf
Added init support to SMV back-end
tree
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commitdiff
2015-06-19
Clifford Wolf
Progress in SMV back-end
tree
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commitdiff
2015-06-19
Clifford Wolf
Progress in SMV back-end
tree
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commitdiff
2015-06-18
Clifford Wolf
Progress in SMV back-end
tree
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commitdiff
2015-06-17
Clifford Wolf
Progress in SMV back-end
tree
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commitdiff
2015-06-17
Clifford Wolf
Progress in SMV back-end
tree
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commitdiff
2015-06-16
Clifford Wolf
Progress in SMV back-end
tree
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commitdiff
2015-06-15
Clifford Wolf
Progress in SMV back-end
tree
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commitdiff
2015-06-15
Clifford Wolf
Progress in SMV back-end
tree
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commitdiff
2015-06-14
Clifford Wolf
Added "write_smv" skeleton
tree
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commitdiff
2015-06-14
Clifford Wolf
Removed debug code from write_smt2
tree
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commitdiff
2015-06-14
Clifford Wolf
Added write_smt2 -mem
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commitdiff
2015-06-11
Clifford Wolf
Fixed cstr_buf for std::string with small string optimi...
tree
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commitdiff
2015-06-11
Clifford Wolf
Improvements in cellaigs.cc and "json -aig"
tree
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commitdiff
2015-06-10
Clifford Wolf
AigMaker refactoring
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commitdiff
2015-06-10
Clifford Wolf
Added "json -aig"
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commitdiff
2015-06-09
Clifford Wolf
Merge branch 'verilog-backend-memV2' of github.com...
tree
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commitdiff
2015-06-08
luke whittlesey
$mem cell in verilog backend : grouped writes by clock
tree
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commitdiff
2015-06-04
luke whittlesey
Bug fix in $mem verilog backend + changed tests/bram...
tree
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commitdiff
2015-05-24
Clifford Wolf
Improvements in BLIF front-end
tree
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commitdiff
2015-05-22
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2015-05-20
Clifford Wolf
Some fixes for $mem in verilog back-end
tree
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commitdiff
2015-05-11
Clifford Wolf
Merge pull request #63 from wluker/verilog-backend-mem
tree
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commitdiff
2015-05-11
luke whittlesey
Fixed bug in $mem cell verilog code generation.
tree
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commitdiff
2015-05-10
Clifford Wolf
Disabled broken $mem support in verilog backend
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commitdiff
2015-05-10
Clifford Wolf
Merge pull request #62 from wluker/verilog-backend-mem
tree
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commitdiff
2015-05-10
luke whittlesey
Made changes recommended by Clifford Wolf ...
tree
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commitdiff
2015-05-08
luke whittlesey
Verilog backend for $mem cells should now be able to...
tree
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commitdiff
2015-05-07
luke whittlesey
Added support for $mem cells in the verilog backend.
tree
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commitdiff
2015-04-09
Clifford Wolf
Minor fixes in handling of "init" attribute
tree
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commitdiff
2015-04-08
Clifford Wolf
Removed "techmap -share_map" (use "-map +/filename...
tree
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commitdiff
2015-04-05
Clifford Wolf
Added "port_directions" to write_json output
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commitdiff
2015-04-04
Clifford Wolf
Added "init" attribute support to verilog backend
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commitdiff
2015-04-04
Clifford Wolf
Merge pull request #55 from ahmedirfan1983/master
tree
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commitdiff
2015-04-03
Ahmed Irfan
Update README
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commitdiff
2015-04-03
Ahmed Irfan
Delete btor.ys
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commitdiff
2015-04-03
Ahmed Irfan
Update README
tree
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commitdiff
2015-04-03
Ahmed Irfan
separated memory next from write cell
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commitdiff
2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
tree
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commitdiff
2015-03-18
Clifford Wolf
Added Verilog backend $dffsr support
tree
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commitdiff
2015-03-06
Clifford Wolf
Documentation for JSON format, added attributes
tree
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commitdiff
2015-03-03
Clifford Wolf
Json bugfix
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commitdiff
2015-03-03
Clifford Wolf
Json backend improvements
tree
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commitdiff
2015-03-02
Clifford Wolf
Added write_blif -attr
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commitdiff
2015-03-02
Clifford Wolf
Added JSON backend
tree
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commitdiff
2015-02-26
Clifford Wolf
Added $assume support to write_smt2
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commitdiff
2015-02-22
Clifford Wolf
Minor "write_smt2" help msg change
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commitdiff
2015-02-22
Clifford Wolf
Added "<mod>_a" and "<mod>_i" to write_smt2 output
tree
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commitdiff
2015-02-13
Clifford Wolf
Fixed "write_verilog -attr2comment" handling of "*...
tree
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commitdiff
2015-02-01
Clifford Wolf
Added EDIF backend support for multi-bit cell ports
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commitdiff
2015-01-31
Clifford Wolf
Shorter "dump" options
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commitdiff
2015-01-24
Clifford Wolf
Added ENABLE_NDEBUG makefile options
tree
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commitdiff
2015-01-23
Clifford Wolf
Added dict/pool.sort()
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commitdiff
2015-01-02
Clifford Wolf
Cosmetic changes in verilog output format
tree
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commitdiff
2015-01-01
Clifford Wolf
Fixed memory->start_offset handling
tree
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commitdiff
2014-12-26
Clifford Wolf
Replaced std::unordered_map as implementation for Yosys...
tree
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commitdiff
2014-12-26
Clifford Wolf
Added Yosys::{dict,nodict,vector} container types
tree
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commitdiff
2014-12-25
Clifford Wolf
Various fixes and improvements in "write_smt2 -bv"
tree
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commitdiff
2014-12-25
Clifford Wolf
Various fixes and improvements in write_smt2
tree
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commitdiff
2014-12-25
Clifford Wolf
Added support for most BV cell types to write_smt2
tree
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commitdiff
2014-12-25
Clifford Wolf
Added "write_smt2 -bv" and other write_smt2 improvements
tree
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commitdiff
2014-12-24
Clifford Wolf
Added write_smt2 (only gate level logic supported so...
tree
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commitdiff
2014-12-24
Clifford Wolf
Renamed extend() to extend_xx(), changed most users...
tree
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commitdiff
2014-12-19
Clifford Wolf
Added $dffe support to write_verilog
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commitdiff
2014-12-19
Clifford Wolf
Fixed another bug in write_blif handling of $lut cells
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commitdiff
2014-12-17
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2014-12-17
Clifford Wolf
Fixed writing of $lut cells in BLIF backend
tree
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commitdiff
2014-12-14
Clifford Wolf
Added "write_blif -undef" and support for special ...
tree
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commitdiff
2014-12-14
Clifford Wolf
Added "write_blif -blackbox"
tree
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commitdiff
2014-12-14
Clifford Wolf
Added "blif -unbuf" feature
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commitdiff
2014-11-09
Clifford Wolf
Added log_warning() API
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commitdiff
2014-11-07
Clifford Wolf
Fixed generation of temp names in verilog backend
tree
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commitdiff
2014-10-10
Clifford Wolf
Renamed SIZE() to GetSize() because of name collision...
tree
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commitdiff
2014-09-27
Clifford Wolf
namespace Yosys
tree
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commitdiff
2014-09-22
Clifford Wolf
Merge pull request #39 from ahmedirfan1983/master
tree
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commitdiff
2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
tree
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commitdiff
2014-09-19
Clifford Wolf
Sorting of object names in ilang backend
tree
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commitdiff
2014-09-18
ahmedirfan1983
fixed memory next issue, when same memory is written...
tree
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commitdiff
2014-09-06
Clifford Wolf
Various bug fixes (related to $macc model testing)
tree
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commitdiff
2014-09-06
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2014-09-06
Clifford Wolf
Merge pull request #38 from rubund/master
tree
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commitdiff
2014-09-06
Ruben Undheim
Corrected spelling mistakes found by lintian
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commitdiff
2014-09-04
Clifford Wolf
Removed $bu0 cell type
tree
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commitdiff
2014-09-03
Clifford Wolf
Using $pos models for $bu0
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commitdiff
2014-09-02
Ahmed Irfan
added $pmux cell translation
tree
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commitdiff
2014-09-01
Clifford Wolf
Using std::vector<RTLIL::State> instead of RTLIL::Const...
tree
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commitdiff
2014-08-23
Clifford Wolf
Changed frontend-api from FILE to std::istream
tree
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commitdiff
2014-08-23
Clifford Wolf
Changed backend-api from FILE to std::ostream
tree
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commitdiff
2014-08-16
Clifford Wolf
Fixed AOI/OAI expr handling in verilog backend
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commitdiff
2014-08-16
Clifford Wolf
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_...
tree
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commitdiff
2014-08-15
Clifford Wolf
Renamed $lut ports to follow A-Y naming scheme
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commitdiff
2014-08-15
Clifford Wolf
Renamed $_INV_ cell type to $_NOT_
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commitdiff
2014-08-14
Clifford Wolf
Refactoring of CellType class
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commitdiff
2014-08-02
Clifford Wolf
Be more conservative with printing decimal numbers...
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commitdiff
2014-08-02
Clifford Wolf
Improved verilog output for ordinary $mux cells
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commitdiff
2014-08-02
Clifford Wolf
No implicit conversion from IdString to anything else
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commitdiff
2014-08-02
Clifford Wolf
More cleanups related to RTLIL::IdString usage
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commitdiff
2014-07-31
Clifford Wolf
Renamed port access function on RTLIL::Cell, added...
tree
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commitdiff
2014-07-31
Clifford Wolf
Moved some stuff to kernel/yosys.{h,cc}, using Yosys...
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commitdiff
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