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Fixes for simple_abc9 tests
[yosys.git]
/
backends
/
2019-04-19
Eddie Hung
Fixes for simple_abc9 tests
tree
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commitdiff
2019-04-19
Eddie Hung
Do not assume inst_module is always present
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commitdiff
2019-04-19
Eddie Hung
ignore_boxes -> holes_mode
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commitdiff
2019-04-19
Eddie Hung
Add flop support for write_xaiger
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commitdiff
2019-04-19
Eddie Hung
Spelling
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commitdiff
2019-04-18
Eddie Hung
Use new -wb flag for ABC flow
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commitdiff
2019-04-18
Eddie Hung
write_json to not write contents (cells/wires) of white...
tree
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commitdiff
2019-04-18
Eddie Hung
Merge remote-tracking branch 'origin/clifford/whitebox...
tree
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commitdiff
2019-04-18
Clifford Wolf
Add "whitebox" attribute, add "read_verilog -wb"
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commitdiff
2019-04-17
Eddie Hung
Fix $anyseq warning and cleanup
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commitdiff
2019-04-17
Eddie Hung
Cope with inout ports
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commitdiff
2019-04-17
Eddie Hung
Stop topological sort at abc_flop_q
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commitdiff
2019-04-17
Eddie Hung
Remove init* from xaiger, also topo-sort cells for...
tree
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commitdiff
2019-04-17
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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commitdiff
2019-04-17
Eddie Hung
Optimise
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commitdiff
2019-04-16
Eddie Hung
CIs before PIs; also sort each cell's connections befor...
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commitdiff
2019-04-16
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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commitdiff
2019-04-16
Eddie Hung
Port from xc7mux branch
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commitdiff
2019-04-16
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
tree
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commitdiff
2019-04-13
Eddie Hung
Output __const0__ and __const1__ CIs
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commitdiff
2019-04-13
Eddie Hung
Merge branch 'xaig' of github.com:YosysHQ/yosys into...
tree
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commitdiff
2019-04-12
Eddie Hung
Merge branch 'xaig' of github.com:YosysHQ/yosys into...
tree
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commitdiff
2019-04-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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commitdiff
2019-04-12
Eddie Hung
ci_bits and co_bits now a list, order is important...
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commitdiff
2019-04-12
Eddie Hung
WIP
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commitdiff
2019-04-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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commitdiff
2019-04-11
Eddie Hung
Add non-input bits driven by unrecognised cells as...
tree
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commitdiff
2019-04-08
Eddie Hung
Merge branch 'master' into xaig
tree
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commitdiff
2019-04-03
Clifford Wolf
Merge pull request #912 from YosysHQ/bram_addr_en
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commitdiff
2019-04-03
Clifford Wolf
Merge pull request #910 from ucb-bar/memupdates
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commitdiff
2019-04-01
Jim Lawson
Refine memory support to deal with general Verilog...
tree
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commitdiff
2019-03-23
Clifford Wolf
Merge pull request #893 from YosysHQ/clifford/btormeminit
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commitdiff
2019-03-23
Clifford Wolf
Add support for memory initialization to write_btor
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commitdiff
2019-03-23
Clifford Wolf
Fix BTOR output tags syntax in writye_btor
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commitdiff
2019-03-19
Eddie Hung
Merge https://github.com/YosysHQ/yosys into read_aiger
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commitdiff
2019-03-14
Clifford Wolf
Merge pull request #875 from YosysHQ/clifford/mutate
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commitdiff
2019-03-14
Clifford Wolf
Fix smtbmc.py handling of zero appended steps
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commitdiff
2019-03-14
Clifford Wolf
Merge pull request #872 from YosysHQ/clifford/pmuxfix
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commitdiff
2019-03-14
Clifford Wolf
Fix a syntax bug in ilang backend related to process...
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commitdiff
2019-03-14
Clifford Wolf
Merge pull request #869 from cr1901/win-shell
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commitdiff
2019-03-13
William D. Jones
Install launcher executable when running yosys-smtbmc...
tree
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commitdiff
2019-03-13
Clifford Wolf
Merge pull request #868 from YosysHQ/clifford/fixmem
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commitdiff
2019-03-12
Clifford Wolf
Merge pull request #866 from YosysHQ/clifford/idstuff
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commitdiff
2019-03-11
Clifford Wolf
Improve determinism of IdString DB for similar scripts
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commitdiff
2019-03-09
Clifford Wolf
Merge pull request #859 from smunaut/ice40_braminit
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commitdiff
2019-03-09
Clifford Wolf
Fix signed $shift/$shiftx handling in write_smt2
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commitdiff
2019-03-09
Clifford Wolf
Merge pull request #858 from YosysHQ/clifford/svalabels
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commitdiff
2019-03-07
Clifford Wolf
Use SVA label in smt export if available
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commitdiff
2019-03-05
Clifford Wolf
Merge pull request #842 from litghost/merge_upstream
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commitdiff
2019-03-05
Clifford Wolf
Merge pull request #850 from daveshah1/ecp5_warn_conflict
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commitdiff
2019-03-05
Clifford Wolf
Merge pull request #851 from kprasadvnsi/master
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commitdiff
2019-03-05
Clifford Wolf
Merge pull request #852 from ucb-bar/firrtlfixes
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commitdiff
2019-03-04
Jim Lawson
Ensure fid() calls make_id() for consistency; tests...
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commitdiff
2019-03-01
Clifford Wolf
Fix "write_edif -gndvccy"
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commitdiff
2019-03-01
Clifford Wolf
Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
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commitdiff
2019-02-28
Clifford Wolf
Merge pull request #834 from YosysHQ/clifford/siminit
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commitdiff
2019-02-28
Clifford Wolf
Add "write_verilog -siminit"
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commitdiff
2019-02-28
Larry Doolittle
Reduce amount of trailing whitespace in code base
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commitdiff
2019-02-28
Clifford Wolf
Merge pull request #794 from daveshah1/ecp5improve
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commitdiff
2019-02-28
Clifford Wolf
Merge pull request #827 from ucb-bar/firrtlfixes
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commitdiff
2019-02-28
Clifford Wolf
Merge pull request #833 from YosysHQ/clifford/fix831
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commitdiff
2019-02-28
Clifford Wolf
Fix smt2 code generation for partially initialized...
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commitdiff
2019-02-26
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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commitdiff
2019-02-26
Eddie Hung
write_xaiger to behave for undriven/unused inouts
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commitdiff
2019-02-26
Eddie Hung
write_xaiger duplicate inout port into out port with...
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commitdiff
2019-02-26
Jim Lawson
Fix FIRRTL to Verilog process instance subfield assignment.
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commitdiff
2019-02-25
Eddie Hung
Cleanup abc9 code
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commitdiff
2019-02-24
Clifford Wolf
Merge pull request #812 from ucb-bar/arrayhierarchyfixes
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commitdiff
2019-02-22
Eddie Hung
write_xaiger to write __dummy_o__ for -symbols too
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commitdiff
2019-02-22
Clifford Wolf
Merge pull request #740 from daveshah1/improve_dress
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commitdiff
2019-02-21
Eddie Hung
Add attribution
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commitdiff
2019-02-21
Eddie Hung
Merge branch 'read_aiger' into xaig
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commitdiff
2019-02-21
Eddie Hung
Merge branch 'read_aiger' into xaig
tree
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commitdiff
2019-02-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
tree
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commitdiff
2019-02-21
Eddie Hung
write_xaiger to use original bit for co, not sigmap...
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commitdiff
2019-02-21
Clifford Wolf
Merge pull request #786 from YosysHQ/pmgen
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commitdiff
2019-02-21
Eddie Hung
Merge branch 'clifford/dffsrfix' of https://github...
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commitdiff
2019-02-21
Eddie Hung
Remove swap file
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commitdiff
2019-02-20
Eddie Hung
write_aiger: fix CI/CO and symbols
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commitdiff
2019-02-20
Eddie Hung
write_xaiger to not write latches, CO/PO fixes
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commitdiff
2019-02-19
Eddie Hung
Merge branch 'master' into xaig
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commitdiff
2019-02-19
Eddie Hung
Merge branch 'master' into read_aiger
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commitdiff
2019-02-19
Eddie Hung
Merge pull request #805 from eddiehung/dff_init
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commitdiff
2019-02-18
Eddie Hung
Merge branch 'dff_init' into read_aiger
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commitdiff
2019-02-17
Eddie Hung
Instead of INIT param on cells, use initial statement...
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commitdiff
2019-02-17
Eddie Hung
Merge https://github.com/YosysHQ/yosys into dff_init
tree
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commitdiff
2019-02-17
Eddie Hung
Merge https://github.com/YosysHQ/yosys into read_aiger
tree
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commitdiff
2019-02-17
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys into...
tree
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commitdiff
2019-02-17
Clifford Wolf
Merge pull request #811 from ucb-bar/firrtlfixes
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commitdiff
2019-02-17
Eddie Hung
Cleanup
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commitdiff
2019-02-17
Eddie Hung
Cleanup
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commitdiff
2019-02-17
Eddie Hung
write_xaiger to support non-bit cell connections, and...
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commitdiff
2019-02-17
Eddie Hung
write_aiger -O to write dummy output as __dummy_o__
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commitdiff
2019-02-16
Eddie Hung
Tidy up write_xaiger
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commitdiff
2019-02-16
Eddie Hung
write_aiger() to perform CI/CO post-processing and...
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commitdiff
2019-02-15
Eddie Hung
Fixes needed for DFF circuits
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commitdiff
2019-02-15
Jim Lawson
Removed unused variables, functions.
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commitdiff
2019-02-15
Eddie Hung
write_xaiger to cope with unknown cells by transforming...
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commitdiff
2019-02-15
Jim Lawson
Update cells supported for verilog to FIRRTL conversion.
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commitdiff
2019-02-14
Eddie Hung
More cleanup
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commitdiff
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