Merge branch 'master' of github.com:YosysHQ/yosys
[yosys.git] / backends /
2019-05-01 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-05-01 Clifford WolfMerge pull request #977 from ucb-bar/fixfirrtlmem
2019-05-01 Jim LawsonFix #938 - Crash occurs in case when use write_firrtl...
2019-04-30 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-04-22 Eddie HungMerge pull request #914 from YosysHQ/xc7srl
2019-04-22 Clifford WolfMerge pull request #952 from YosysHQ/clifford/fix370
2019-04-22 Clifford WolfMerge pull request #951 from YosysHQ/clifford/logdebug
2019-04-22 Clifford WolfMerge pull request #949 from YosysHQ/clifford/pmux2shim...
2019-04-22 Clifford WolfMerge pull request #953 from YosysHQ/clifford/fix948
2019-04-22 Clifford WolfAdd support for zero-width signals to Verilog back...
2019-04-22 Clifford WolfMerge pull request #905 from christian-krieg/feature...
2019-04-22 Clifford WolfMerge pull request #941 from Wren6991/sim_lib_io_clke
2019-04-22 Clifford WolfMerge branch 'master' of https://github.com/dh73/yosys_...
2019-04-22 Clifford WolfMerge pull request #911 from mmicko/gowin-nobram
2019-04-22 Clifford WolfMerge pull request #909 from zachjs/master
2019-04-22 Clifford WolfMerge pull request #944 from YosysHQ/clifford/pmux2shiftx
2019-04-21 Eddie HungMerge branch 'master' into map_cells_before_map_luts
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/clifford/pmux2shif...
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-20 Clifford WolfMerge pull request #943 from YosysHQ/clifford/whitebox
2019-04-20 Eddie HungMerge remote-tracking branch 'origin/pmux2shiftx' into...
2019-04-20 Eddie HungMerge remote-tracking branch 'origin' into xc7srl
2019-04-20 Clifford WolfMerge pull request #942 from YosysHQ/clifford/fix931
2019-04-19 Clifford WolfChange "ne" to "neq" in btor2 output
2019-04-19 Eddie HungRevert "write_json to not write contents (cells/wires...
2019-04-18 Eddie Hungwrite_json to not write contents (cells/wires) of white...
2019-04-18 Clifford WolfAdd "whitebox" attribute, add "read_verilog -wb"
2019-04-03 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-03 Clifford WolfMerge pull request #912 from YosysHQ/bram_addr_en
2019-04-03 Clifford WolfMerge pull request #910 from ucb-bar/memupdates
2019-04-01 Jim LawsonRefine memory support to deal with general Verilog...
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2019-03-25 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-23 Clifford WolfMerge pull request #893 from YosysHQ/clifford/btormeminit
2019-03-23 Clifford WolfAdd support for memory initialization to write_btor
2019-03-23 Clifford WolfFix BTOR output tags syntax in writye_btor
2019-03-19 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-03-14 Clifford WolfMerge pull request #875 from YosysHQ/clifford/mutate
2019-03-14 Clifford WolfFix smtbmc.py handling of zero appended steps
2019-03-14 Clifford WolfMerge pull request #872 from YosysHQ/clifford/pmuxfix
2019-03-14 Clifford WolfFix a syntax bug in ilang backend related to process...
2019-03-14 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-14 Clifford WolfMerge pull request #869 from cr1901/win-shell
2019-03-13 William D. JonesInstall launcher executable when running yosys-smtbmc...
2019-03-13 Clifford WolfMerge pull request #868 from YosysHQ/clifford/fixmem
2019-03-12 Clifford WolfMerge pull request #866 from YosysHQ/clifford/idstuff
2019-03-11 Clifford WolfImprove determinism of IdString DB for similar scripts
2019-03-09 Clifford WolfMerge pull request #859 from smunaut/ice40_braminit
2019-03-09 Clifford WolfFix signed $shift/$shiftx handling in write_smt2
2019-03-09 Clifford WolfMerge pull request #858 from YosysHQ/clifford/svalabels
2019-03-07 Clifford WolfUse SVA label in smt export if available
2019-03-05 Clifford WolfMerge pull request #842 from litghost/merge_upstream
2019-03-05 Clifford WolfMerge pull request #850 from daveshah1/ecp5_warn_conflict
2019-03-05 Clifford WolfMerge pull request #851 from kprasadvnsi/master
2019-03-05 Clifford WolfMerge pull request #852 from ucb-bar/firrtlfixes
2019-03-04 Jim LawsonEnsure fid() calls make_id() for consistency; tests...
2019-03-01 Clifford WolfFix "write_edif -gndvccy"
2019-03-01 Clifford WolfMerge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
2019-02-28 Clifford WolfMerge pull request #834 from YosysHQ/clifford/siminit
2019-02-28 Clifford WolfAdd "write_verilog -siminit"
2019-02-28 Larry DoolittleReduce amount of trailing whitespace in code base
2019-02-28 Clifford WolfMerge pull request #794 from daveshah1/ecp5improve
2019-02-28 Clifford WolfMerge pull request #827 from ucb-bar/firrtlfixes
2019-02-28 Clifford WolfMerge pull request #833 from YosysHQ/clifford/fix831
2019-02-28 Clifford WolfFix smt2 code generation for partially initialized...
2019-02-26 Jim LawsonFix FIRRTL to Verilog process instance subfield assignment.
2019-02-24 Clifford WolfMerge pull request #812 from ucb-bar/arrayhierarchyfixes
2019-02-22 Clifford WolfMerge pull request #740 from daveshah1/improve_dress
2019-02-21 Clifford WolfMerge pull request #786 from YosysHQ/pmgen
2019-02-19 Eddie HungMerge pull request #805 from eddiehung/dff_init
2019-02-18 Eddie HungMerge branch 'dff_init' into read_aiger
2019-02-17 Eddie HungInstead of INIT param on cells, use initial statement...
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into dff_init
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-02-17 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-02-17 Clifford WolfMerge pull request #811 from ucb-bar/firrtlfixes
2019-02-15 Jim LawsonRemoved unused variables, functions.
2019-02-15 Jim LawsonUpdate cells supported for verilog to FIRRTL conversion.
2019-02-12 Clifford WolfMerge pull request #802 from whitequark/write_verilog_a...
2019-02-08 Eddie HungMerge remote-tracking branch 'origin/dff_init' into...
2019-02-06 Eddie HungRemove check for cell->name[0] == '$'
2019-02-06 Eddie HungMerge branch 'dff_init' of https://github.com/eddiehung...
2019-02-06 Eddie HungRefactor
2019-02-06 Eddie Hungwrite_verilog to cope with init attr on q when -noexpr
2019-02-06 Clifford WolfAdd missing blackslash-to-slash convertion to smtio...
2019-01-29 whitequarkwrite_verilog: correctly emit asynchronous transparent...
2019-01-27 Clifford WolfMerge pull request #798 from mmicko/master
2019-01-27 Clifford WolfMerge pull request #800 from whitequark/write_verilog_t...
2019-01-27 Clifford WolfMerge branch 'whitequark-write_verilog_keyword'
2019-01-27 whitequarkwrite_verilog: write $tribuf cell as ternary.
2019-01-27 whitequarkwrite_verilog: escape names that match SystemVerilog...
2019-01-17 Clifford WolfAdd "write_edif -gndvccy"
2019-01-15 Clifford WolfFix handling of $shiftx in Verilog back-end
2019-01-02 Clifford WolfMerge pull request #770 from whitequark/opt_expr_cmp
2019-01-02 Clifford WolfMerge pull request #755 from Icenowy/anlogic-dram-init
2019-01-02 Clifford WolfMerge pull request #750 from Icenowy/anlogic-ff-init
2019-01-02 Clifford WolfMerge pull request #773 from whitequark/opt_lut_elim_fixes
2019-01-02 Clifford WolfMerge pull request #772 from whitequark/synth_lut
2019-01-02 Clifford WolfMerge pull request #771 from whitequark/techmap_cmp2lut
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