sim, kvm: make KvmVM a System parameter
[gem5.git] / configs / example / se.py
2017-02-14 Curtis Dunhamsim, kvm: make KvmVM a System parameter
2016-10-14 Andreas Hanssonconfig: Make configs/common a Python package
2016-10-13 Andreas Hanssonruby: Fix regressions and make Ruby configs Python...
2016-10-06 Tushar Krishnaconfig: add a separate config file for the network.
2015-12-07 Radhika Jagtapconfig: Enable elastic trace capture and replay in...
2015-09-30 Mitch Hayengaisa,cpu: Add support for FS SMT Interrupts
2015-09-30 Mitch Hayengaconfig,cpu: Add SMT support to Atomic and Timing CPUs
2015-09-07 Nilay Vaishconfig: allow ruby to be used with Minor CPU
2015-04-23 bpotterconfig: enable setting SE-mode environment variables...
2015-03-02 Andreas Hanssonmem: Move crossbar default latencies to subclasses
2015-01-20 Andreas Hanssonscons: Do not build the InOrderCPU
2014-11-24 Alexandru Dutuconfig, kvm: Enabling KvmCPU in SE mode
2014-11-19 Nilay Vaishconfigs: small fix to ruby portion of fs.py and se.py
2014-11-06 Nilay Vaishruby: interface with classic memory controller
2014-11-06 Nilay Vaishruby: single physical memory in fs mode
2014-09-20 Andreas Hanssonmem: Rename Bus to XBar to better reflect its behaviour
2014-09-20 Dam Sunwoocpu: use probes infrastructure to do simpoint profiling
2014-09-01 Emilio Castillo... ruby: Fixes clock domains in configuration files
2014-04-01 Nilay Vaishconfigs: use SimpleMemory when using ruby in se mode
2014-03-20 Nilay Vaishconfig: ruby: rename _cpu_ruby_ports to _cpu_ports
2014-03-20 Nilay Vaishconfig: remove ruby_fs.py
2014-03-20 Nilay Vaishruby: no piobus in se mode
2014-02-25 Nilay Vaishruby: correct errors in changeset 4eec7bdde5b0
2014-01-24 ARM gem5 Developersarm: Add support for ARMv8 (AArch64 & AArch32)
2013-10-07 Nilay Vaishconfig: set cwd for processes in se.py
2013-08-19 Andreas Hanssonconfig: Command line support for multi-channel memory
2013-08-19 Akash Bagdiapower: Add voltage domains to the clock domains
2013-07-18 Andreas Hanssonconfig: Update script to set cache line size on system
2013-06-29 Nilay Vaishconfigs: rearrange the available options in Options.py
2013-06-27 Akash Bagdiasim: Add the notion of clock domains to all ClockedObjects
2013-06-27 Akash Bagdiaconfig: Add a system clock command-line option
2013-06-27 Akash Bagdiaconfig: Add a CPU clock command-line option
2013-06-13 Nilay Vaishconfig: Do not instantiate membus when using ruby
2013-04-22 Andreas Hanssonconfig: Add a mem-type config option to se/fs scripts
2013-04-22 Dam Sunwoocpu: generate SimPoint basic block vector profiles
2013-03-07 Nilay Vaishruby: remove the functional copy of memory in se mode
2013-01-07 Andreas Sandbergarch: Make the ISA class inherit from SimObject
2012-10-26 Andreas Hanssonconfig: Add a check for fastmem only used with Atomic CPU
2012-09-28 Malek MuslehConfigs: SE script fix for Alpha and Ruby simulations
2012-09-13 Joel Hestnessse.py Ruby: Connect TLB walker ports
2012-09-11 Nilay Vaishse.py: removes error in passing options to a binary
2012-09-09 Nilay Vaishse.py: support specifying multiple programs via command...
2012-07-23 Andreas HanssonConfig: Use clock option in se/fs script and pass to...
2012-07-11 Brad Beckmannruby: changes how Topologies are created
2012-05-31 Andreas HanssonBus: Split the bus into a non-coherent and coherent bus
2012-05-16 Andreas HanssonConfig: Fix a typo in the se.py script for setting...
2012-04-17 Jayneel GandhiSE Config: Changed se.py to support multithreaded mode
2012-04-06 Andreas HanssonMEM: Enable multiple distributed generalized memories
2012-04-03 Andreas HanssonAtomic: Remove the physmem_port and access memory directly
2012-03-28 Nilay VaishConfig: Change the way options are added
2012-03-11 Nilay Vaishse.py: Changes to ruby portion due to SE/FS merge
2012-03-09 Geoffrey BlakeCheckerCPU: Make CheckerCPU runtime selectable instead...
2012-03-01 Nilay VaishConfig: make option ruby available always
2012-02-14 Andreas HanssonMEM: Fix master/slave ports in Ruby and non-regression...
2012-02-13 Andreas HanssonMEM: Introduce the master/slave port roles in the Pytho...
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Gabe BlackMerge with main repository.
2012-01-30 Andreas HanssonRuby: Connect system port in Ruby network test
2012-01-29 Gabe BlackYet another merge with the main repository.
2012-01-28 Gabe BlackSE/FS: Get rid of FULL_SYSTEM in the configs directory
2012-01-28 Gabe BlackSE/FS: Make SE vs. FS mode a runtime parameter.
2012-01-28 Gabe BlackMerge with the main repo.
2012-01-23 Nilay VaishConfig: Enable using O3 CPU and Ruby in SE mode
2012-01-17 Andreas HanssonMEM: Add port proxies instead of non-structural ports
2012-01-07 Gabe BlackAnother merge with the main repository.
2012-01-05 Nilay VaishConfig: Add an option of type 'choice' for cpu type
2011-08-02 Nilay VaishScons: Drop RUBY as compile time option.
2011-07-12 Nilay Vaishse.py: Fixes the way ruby's options are added
2011-07-01 Brad Beckmann ext... Ruby: Add support for functional accesses
2011-05-23 Steve Reinhardtconfig: tweak ruby configs to clean up hierarchy
2011-03-20 Lisa Hsuconfigs: combine ruby_se.py and se.py to avoid all...
2011-03-20 Lisa Hsuenable x86 workloads on se.py
2011-03-20 Lisa Hsuse.py: Modify script to make multiprogramming much...
2010-12-08 Ali SaidiConfigs: Automatically choose the correct hello world...
2010-02-25 Lisa Hsuconfigs: pull out cache configuration code from se...
2010-02-23 Lisa Hsucache: Make caches sharing aware and add occupancy...
2010-01-19 Derek Howermerge
2009-09-22 Nathan Binkertpython: Move more code into m5.util allow SCons to...
2009-09-16 Korey Sewellinorder-configs: update se.py
2009-08-03 Derek HowerAutomated merge with ssh://hg@m5sim.org/m5
2009-07-26 Korey Sewellse-configs: edit se.py to account for non-O3CPU workloads
2009-07-25 Korey Sewello3-smt: enforce numThreads parameter for SMT SE mode
2009-04-06 Gabe BlackMerge ARM into the head. ARM will compile but may not...
2009-01-31 Ali SaidiErrors: Print a URL with a hash of the format string...
2008-07-23 Michael Adlerprocess: separate stderr from stdout
2008-06-13 Steve ReinhardtAutomated merge with ssh://m5sim.org//repo/m5
2008-06-13 Ali SaidiScripts: Check for the appropriate build type as soon...
2008-02-29 Ali SaidiConfigs: Fix some bugs we introduced in the simpoints...
2007-09-06 Gabe BlackMerge with head.
2007-09-05 Ali SaidiConfiguration: Fix example script to only create one...
2007-08-14 Ali SaidiMerge IGNORE_STYLE change and my change.
2007-08-12 Nathan Binkertmerge
2007-08-08 Vincentius RobbyAdded fastmem option.
2007-08-03 Steve Reinhardtmerge from head
2007-08-02 Ali Saidimerge, no manual changes
2007-08-02 Gabe BlackFix how the "cmd" parameter is set in se.py and remove...
2007-06-20 Gabe BlackMerge zizzer.eecs.umich.edu:/bk/newmem
2007-05-19 Steve ReinhardtMerge vm1.(none):/home/stever/bk/newmem-head
2007-05-18 Gabe BlackMerge zizzer.eecs.umich.edu:/bk/newmem
2007-05-15 Ali SaidiMerge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
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