sim: Make it possible to override the breakpoint length check.
[gem5.git] / configs / example /
2014-11-24 Alexandru Dutuconfig, kvm: Enabling KvmCPU in SE mode
2014-11-19 Nilay Vaishconfigs: small fix to ruby portion of fs.py and se.py
2014-11-06 Nilay Vaishruby: interface with classic memory controller
2014-11-06 Nilay Vaishruby: single physical memory in fs mode
2014-10-30 Ali Saidiautomated merge
2014-10-30 Ali Saidiarm, tests: Update config files to more recent kernels...
2014-10-16 Andreas Hanssonconfig: Add the ability to read a config file using...
2014-09-20 Andreas Hanssonmem: Rename Bus to XBar to better reflect its behaviour
2014-09-20 Dam Sunwoocpu: use probes infrastructure to do simpoint profiling
2014-09-01 Emilio Castillo... ruby: Fixes clock domains in configuration files
2014-08-10 Radhika Jagtapconfig: Fix cache latency param in mem test
2014-04-01 Nilay Vaishconfigs: use SimpleMemory when using ruby in se mode
2014-03-20 Nilay Vaishconfig: ruby: rename _cpu_ruby_ports to _cpu_ports
2014-03-20 Nilay Vaishconfig: fs.py: move creating of test/drive systems...
2014-03-20 Nilay Vaishconfig: remove ruby_fs.py
2014-03-20 Nilay Vaishruby: no piobus in se mode
2014-02-25 Nilay Vaishruby: correct errors in changeset 4eec7bdde5b0
2014-02-24 Nilay Vaishruby: route all packets through ruby port
2014-02-21 Nilay Vaishconfig: ruby_random_test: updates due to recent unrelat...
2014-01-31 Nilay Vaishconfig: correct bug in x86 drive sys instantiation
2014-01-28 Nilay Vaishconfig: allow more than 3GB of memory for x86 simulations
2014-01-24 ARM gem5 Developersarm: Add support for ARMv8 (AArch64 & AArch32)
2013-10-17 Dam Sunwooutil: Streamline .apc project convertsion script
2013-10-17 Ali Saidiconfig: Fix memtest example script
2013-10-09 Nilay Vaishconfig: correct example ruby scripts
2013-10-07 Nilay Vaishconfig: set cwd for processes in se.py
2013-09-18 Joel Hestnessconfigs: Fix ruby_fs.py cache line size
2013-09-12 Andreas Hanssonconfig: Add voltage domain to Ruby example scripts
2013-08-19 Andreas Hanssonconfig: Command line support for multi-channel memory
2013-08-19 Andreas Hanssonmem: Change AbstractMemory defaults to match the common...
2013-08-19 Akash Bagdiapower: Add voltage domains to the clock domains
2013-08-19 Andreas Hanssonconfig: Move the memory instantiation outside FSConfig
2013-07-18 Andreas Hanssonconfig: Update script to set cache line size on system
2013-06-29 Nilay Vaishconfigs: rearrange the available options in Options.py
2013-06-27 Akash Bagdiasim: Add the notion of clock domains to all ClockedObjects
2013-06-27 Akash Bagdiaconfig: Add a system clock command-line option
2013-06-27 Akash Bagdiaconfig: Add a CPU clock command-line option
2013-06-27 Akash Bagdiaconfig: Remove redundant explicit setting of default...
2013-06-13 Nilay Vaishconfig: Do not instantiate membus when using ruby
2013-04-23 Marco Elverconfig: Fix mem-type option not used in ruby_fs script
2013-04-22 Andreas Hanssonconfig: Add a mem-type config option to se/fs scripts
2013-04-22 Andreas Sandbergconfig: Add a KVM VM to systems with KVM CPUs
2013-04-22 Dam Sunwoocpu: generate SimPoint basic block vector profiles
2013-03-07 Nilay Vaishruby: remove the functional copy of memory in se mode
2013-02-15 Anthony Gutierrezoptions: add command line option for dtb file
2013-01-07 Andreas Hanssonconfig: Do not use hardcoded physmem in fs script
2013-01-07 Andreas Sandbergarch: Make the ISA class inherit from SimObject
2012-12-11 Nilay Vaishruby: modify the directed tester to read/write streams
2012-10-26 Andreas Hanssonconfig: Add a check for fastmem only used with Atomic CPU
2012-10-26 Andreas Hanssonconfig: Remove unused mem_size in fs.py
2012-10-15 Nilay Vaishruby: improved support for functional accesses
2012-10-15 Andreas HanssonMem: Use cycles to express cache-related latencies
2012-09-28 Malek MuslehConfigs: SE script fix for Alpha and Ruby simulations
2012-09-27 Andreas HanssonConfigs: Fix memtest cache latency to match new parameters
2012-09-27 Andreas HanssonConfigs: Fix memtest.py by moving the system port
2012-09-13 Joel Hestnessse.py Ruby: Connect TLB walker ports
2012-09-11 Nilay Vaishse.py: removes error in passing options to a binary
2012-09-09 Nilay Vaishse.py: support specifying multiple programs via command...
2012-08-22 Andreas HanssonBridge: Remove NACKs in the bridge and unify with packe...
2012-07-23 Andreas HanssonConfig: Use clock option in se/fs script and pass to...
2012-07-12 Andreas HanssonMem: Make SimpleMemory single ported
2012-07-11 Brad Beckmannruby: remove the cpu assumptions for the random tester
2012-07-11 Brad Beckmannruby: changes how Topologies are created
2012-06-07 Nilay VaishConfig: call to setWorkCountOptions() for all ISAs
2012-06-07 Nilay VaishConfig: Remove setMipsOptions
2012-06-07 Nilay VaishConfig: changes to a couple of error msgs
2012-05-31 Andreas HanssonBus: Split the bus into a non-coherent and coherent bus
2012-05-16 Andreas HanssonConfig: Fix a typo in the se.py script for setting...
2012-04-17 Jayneel GandhiSE Config: Changed se.py to support multithreaded mode
2012-04-16 Jayneel GandhiConfig: Add command line options for disk image and...
2012-04-06 Brad Beckmannrubytest: seperated read and write ports.
2012-04-06 Andreas HanssonMEM: Enable multiple distributed generalized memories
2012-04-05 Nilay VaishConfig: corrects the way Ruby attaches to the DMA ports
2012-04-05 Andreas HanssonRuby: Fix the example configurations option parsing
2012-04-03 Andreas HanssonAtomic: Remove the physmem_port and access memory directly
2012-03-28 Nilay VaishConfig: Change the way options are added
2012-03-27 Nilay VaishConfig: Move setWorkCountOptions() to Simulation.py
2012-03-16 Nilay Vaishruby_fs.py: Add call to createInterruptController()
2012-03-11 Nilay Vaishse.py: Changes to ruby portion due to SE/FS merge
2012-03-09 Ali SaidiARM: Fix memory starting at non-zero address and exceed...
2012-03-09 Geoffrey BlakeCheckerCPU: Make CheckerCPU runtime selectable instead...
2012-03-09 Ali Saidicache: Allow main memory to be at disjoint address...
2012-03-01 Ali SaidiARM: Add support for Versatile Express extended memory map
2012-03-01 Nilay Vaishx86: Fix switching of CPUs
2012-03-01 Nilay VaishConfig: make option ruby available always
2012-02-14 Andreas HanssonMEM: Fix residual bus ports and make them master/slave
2012-02-14 Andreas HanssonMEM: Fix master/slave ports in Ruby and non-regression...
2012-02-13 Andreas HanssonMEM: Introduce the master/slave port roles in the Pytho...
2012-02-01 Ali Saidiconfigs: More fixes for the memory system updates
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Gabe BlackMerge with main repository.
2012-01-30 Andreas HanssonRuby: Connect system port in Ruby network test
2012-01-29 Gabe BlackYet another merge with the main repository.
2012-01-29 Nilay VaishConfig: Enable O3 CPU and Ruby in FS mode
2012-01-28 Gabe BlackSE/FS: Get rid of FULL_SYSTEM in the configs directory
2012-01-28 Gabe BlackSE/FS: Make SE vs. FS mode a runtime parameter.
2012-01-28 Gabe BlackMerge with the main repo.
2012-01-25 Andreas HanssonMEM: Fix fs.py by specifying the range size rather...
2012-01-16 Gabe BlackMerge yet again with the main repository.
2012-01-23 Nilay VaishConfig: Enable using O3 CPU and Ruby in SE mode
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