Improve architectural compliance of mfspr and mtspr
[microwatt.git] / dcache.vhdl
2020-05-06 Anton BlanchardMerge pull request #166 from paulusmack/master
2020-05-06 Paul MackerrasMerge remote-tracking branch 'remotes/origin/master'
2020-05-06 Paul Mackerrasdcache: Don't assert on dcbz cache hit
2020-04-28 Paul Mackerrasdcache: Implement the dcbz instruction
2020-03-30 Anton BlanchardMerge pull request #153 from paulusmack/master
2020-03-28 Paul Mackerrasloadstore1: Move logic from dcache to loadstore1
2020-03-05 Paul Mackerrasdcache: Remove LOAD_UPDATE2 state
2020-03-04 Paul Mackerrasdcache: Trim one cycle from the load hit path
2020-02-27 Paul Mackerrasdcache: Implement load-reserve and store-conditional...
2020-02-26 Paul Mackerrasdcache: Add support for unaligned loads and stores
2020-02-21 Paul Mackerrasdcache: Fix obscure bug and minor cleanups
2019-12-09 Anton BlanchardMerge pull request #122 from paulusmack/benh-sprs
2019-12-07 Benjamin HerrenschmidtAdd basic XER support
2019-11-15 Anton BlanchardMerge pull request #118 from antonblanchard/bus-pipeline
2019-10-30 Benjamin HerrenschmidtMove log2/ispow2 to a utils package
2019-10-30 Benjamin Herrenschmidtdcache: Add wishbone pipelining support
2019-10-25 Anton BlanchardMerge pull request #115 from antonblanchard/reduce...
2019-10-25 Anton BlanchardMerge pull request #113 from mikey/exec-sim-remove
2019-10-25 Anton BlanchardMerge pull request #114 from antonblanchard/dcache
2019-10-23 Benjamin HerrenschmidtMake it possible to change wishbone address size
2019-10-23 Benjamin Herrenschmidticache & dcache: Fix store way variable
2019-10-23 Benjamin Herrenschmidtdcache: Cleanup (mostly cosmetic)
2019-10-23 Benjamin Herrenschmidtdcache: Introduce an extra cycle latency to make timing
2019-10-23 Benjamin Herrenschmidtdcache: Add a dcache