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back.verilog: remove debug code.
[nmigen.git] / examples / ctrl.py
2018-12-13 whitequarkfhdl.ir: implement clock domain propagation. blob | commitdiff | raw
2018-12-12 whitequarkfhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix. blob | commitdiff | raw | diff to current
2018-12-12 whitequarkInitial commit. blob | commitdiff | raw | diff to current