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Add "min bits" and "min wports" to xilinx dram rules
[yosys.git] / examples / python-api /
2019-04-30 Jim LawsonMerge remote-tracking branch 'upstream/master' tree | commitdiff
2019-04-22 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl tree | commitdiff
2019-04-22 Clifford WolfMerge pull request #905 from christian-krieg/feature... tree | commitdiff
2019-04-03 Benedikt TutzerAdded cell_stats example tree | commitdiff
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu... tree | commitdiff
2018-12-11 Benedikt TutzerAdded sample code for python-api tree | commitdiff