2019-12-02 |
whitequark | hdl.ast: actually remove simulator commands. |
tree | commitdiff |
2019-11-28 |
whitequark | back.pysim: redesign the simulator. |
tree | commitdiff |
2019-10-26 |
whitequark | back.rtlil: fix lowering of Part() on LHS to account... |
tree | commitdiff |
2019-10-11 |
whitequark | hdl.ast: deprecate Signal.{range,enum}. |
tree | commitdiff |
2019-10-09 |
whitequark | examples: update blinky, add some explanatory text... |
tree | commitdiff |
2019-09-23 |
whitequark | lib.cdc: MultiReg→FFSynchronizer. |
tree | commitdiff |
2019-09-08 |
whitequark | hdl.mem,lib,examples: use Signal.range(). |
tree | commitdiff |
2019-09-06 |
whitequark | Remove nmigen.lib from prelude. |
tree | commitdiff |
2019-08-22 |
Reto Kramer | examples/basic/uart: document `divisor` parameter. |
tree | commitdiff |
2019-08-12 |
whitequark | hdl.xfrm: CEInserter→EnableInserter. |
tree | commitdiff |
2019-07-08 |
whitequark | test: generate examples to verilog as part of unit... |
tree | commitdiff |
2019-07-08 |
whitequark | examples/basic/ctr_ce: fix outdated syntax. |
tree | commitdiff |
2019-06-27 |
whitequark | examples: add concise UART example. |
tree | commitdiff |
2019-06-04 |
whitequark | vendor.board: split off into nmigen-boards package. |
tree | commitdiff |
2019-06-03 |
whitequark | examples: reorganize into examples/basic and examples... |
tree | commitdiff |
2019-06-03 |
whitequark | vendor.board: extract package. |
tree | commitdiff |
2019-06-03 |
whitequark | build.res: if not specified, request resource #0. |
tree | commitdiff |
2019-06-01 |
whitequark | vendor.ice40_hx1k_blink_evn: implement. |
tree | commitdiff |
2019-04-21 |
whitequark | Remove examples/tbuf.py. |
tree | commitdiff |
2019-04-21 |
whitequark | hdl.ir: detect elaboratables that are created but not... |
tree | commitdiff |
2019-03-12 |
Alain Péteut | examples.por: fix typo |
tree | commitdiff |
2019-01-26 |
whitequark | examples: update for newer API. |
tree | commitdiff |
2019-01-26 |
whitequark | hdl.ir: rename .get_fragment() to .elaborate(). |
tree | commitdiff |
2019-01-14 |
whitequark | lib.io: lower to platform-independent tristate buffer. |
tree | commitdiff |
2019-01-14 |
whitequark | hdl: make ClockSignal and ResetSignal usable on LHS. |
tree | commitdiff |
2018-12-28 |
whitequark | hdl.rec: add basic record support. |
tree | commitdiff |
2018-12-27 |
whitequark | hdl.dsl: add support for fsm.ongoing(). |
tree | commitdiff |
2018-12-26 |
whitequark | examples: add an FSM usage example (UART receiver). |
tree | commitdiff |
2018-12-23 |
whitequark | cli: new module, for basic design generaton/simulation. |
tree | commitdiff |
2018-12-21 |
whitequark | hdl.mem: tie rdport.en high for asynchronous or transpa... |
tree | commitdiff |
2018-12-21 |
whitequark | back.rtlil: implement memories. |
tree | commitdiff |
2018-12-20 |
whitequark | ir: allow non-Signals in Instance ports. |
tree | commitdiff |
2018-12-17 |
whitequark | fhdl.ir: add black-box fragments, fragment parameters... |
tree | commitdiff |
2018-12-17 |
whitequark | back.rtlil: implement Array. |
tree | commitdiff |
2018-12-15 |
whitequark | examples: rename clkdiv/ctrl to ctr/ctr_ce. |
tree | commitdiff |
2018-12-15 |
whitequark | Move star imports to make `from nmigen import *` usable. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: Simulator({gtkw_signals→traces}=). |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: more general clean-up. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: if requested, write a gtkw file with a... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: implement "sync processes", like migen... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: allow suspending processes until a tick... |
tree | commitdiff |
2018-12-13 |
whitequark | back.pysim: fix handling of process termination. |
tree | commitdiff |
2018-12-13 |
whitequark | back.pysim: new simulator backend (WIP). |
tree | commitdiff |
2018-12-13 |
whitequark | fhdl, back: trace and emit source locations of values. |
tree | commitdiff |
2018-12-13 |
whitequark | fhdl.ir: implement clock domain propagation. |
tree | commitdiff |
2018-12-13 |
whitequark | fhdl.dsl: use less error-prone Switch/Case two-level... |
tree | commitdiff |
2018-12-12 |
whitequark | fhdl.ir: fix port threading code. |
tree | commitdiff |
2018-12-12 |
whitequark | fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix. |
tree | commitdiff |
2018-12-12 |
whitequark | genlib.cdc.MultiReg: pull in from Migen. |
tree | commitdiff |
2018-12-12 |
whitequark | ClockDomain.{rst→reset}, for consistency with ResetInse... |
tree | commitdiff |
2018-12-12 |
whitequark | Initial commit. |
tree | commitdiff |
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