Add a name to timing_checker submodule
[gram.git] / examples /
2020-07-10 Jean THOMASRework headless client interface
2020-07-09 Jean THOMASMake power-on delay signal synchronous
2020-07-09 Jean THOMASFix formatting in headless example
2020-07-08 Jean THOMASUpdate memtest code
2020-07-07 Jean THOMASFix CRG PLL parameters (fixing #23)
2020-07-03 Jean THOMASUse CRG parameters that actually work on hardware
2020-06-25 Jean THOMASSet UART bridge SEL signals to 0xF
2020-06-22 Jean THOMASRollback to the ECP5 P/N used in ECPIX-5
2020-06-22 Jean THOMASFix pinout
2020-06-17 Jean THOMASRemove lambdasoc dependency from UARTBridge
2020-06-16 Jean THOMASAdd example code for headless SoC
2020-06-12 Jean THOMASAdd while(1) loop to firmware
2020-06-11 Jean THOMASRename sys2x to sync2x
2020-06-11 Jean THOMASFix comparison value
2020-06-11 Jean THOMASMake memory test code more verbose
2020-06-10 Jean THOMASAdd test firmware
2020-06-10 Jean THOMASFix missing submodule statement in ECPIX5 example
2020-06-09 Jean THOMASAutopep8 on example code
2020-06-09 Jean THOMASRework LiteDRAM wishbone frontend (wip)
2020-06-08 Jean THOMASConnect dramcore to SoC bus in ECPIX-5 example
2020-06-08 Jean THOMASFix PLL
2020-06-04 Jean THOMASAdd dram core as submodule
2020-06-04 Jean THOMASAdd second clock
2020-06-04 Jean THOMASRemove diff pairs in ECPIX5Platform
2020-06-03 Jean THOMASInitial commit