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build.{dsl,plat,res}: allow dir="oe".
[nmigen.git]
/
examples
/
2019-06-03
whitequark
build.res: if not specified, request resource #0.
tree
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commitdiff
2019-06-01
whitequark
vendor.ice40_hx1k_blink_evn: implement.
tree
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commitdiff
2019-04-21
whitequark
Remove examples/tbuf.py.
tree
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commitdiff
2019-04-21
whitequark
hdl.ir: detect elaboratables that are created but not...
tree
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commitdiff
2019-03-12
Alain Péteut
examples.por: fix typo
tree
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commitdiff
2019-01-26
whitequark
examples: update for newer API.
tree
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commitdiff
2019-01-26
whitequark
hdl.ir: rename .get_fragment() to .elaborate().
tree
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commitdiff
2019-01-14
whitequark
lib.io: lower to platform-independent tristate buffer.
tree
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commitdiff
2019-01-14
whitequark
hdl: make ClockSignal and ResetSignal usable on LHS.
tree
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commitdiff
2018-12-28
whitequark
hdl.rec: add basic record support.
tree
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commitdiff
2018-12-27
whitequark
hdl.dsl: add support for fsm.ongoing().
tree
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commitdiff
2018-12-26
whitequark
examples: add an FSM usage example (UART receiver).
tree
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commitdiff
2018-12-23
whitequark
cli: new module, for basic design generaton/simulation.
tree
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commitdiff
2018-12-21
whitequark
hdl.mem: tie rdport.en high for asynchronous or transpa...
tree
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commitdiff
2018-12-21
whitequark
back.rtlil: implement memories.
tree
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commitdiff
2018-12-20
whitequark
ir: allow non-Signals in Instance ports.
tree
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commitdiff
2018-12-17
whitequark
fhdl.ir: add black-box fragments, fragment parameters...
tree
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commitdiff
2018-12-17
whitequark
back.rtlil: implement Array.
tree
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commitdiff
2018-12-15
whitequark
examples: rename clkdiv/ctrl to ctr/ctr_ce.
tree
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commitdiff
2018-12-15
whitequark
Move star imports to make `from nmigen import *` usable.
tree
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commitdiff
2018-12-14
whitequark
back.pysim: Simulator({gtkw_signals→traces}=).
tree
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commitdiff
2018-12-14
whitequark
back.pysim: more general clean-up.
tree
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commitdiff
2018-12-14
whitequark
back.pysim: if requested, write a gtkw file with a...
tree
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commitdiff
2018-12-14
whitequark
back.pysim: implement "sync processes", like migen...
tree
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commitdiff
2018-12-14
whitequark
back.pysim: allow suspending processes until a tick...
tree
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commitdiff
2018-12-13
whitequark
back.pysim: fix handling of process termination.
tree
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commitdiff
2018-12-13
whitequark
back.pysim: new simulator backend (WIP).
tree
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commitdiff
2018-12-13
whitequark
fhdl, back: trace and emit source locations of values.
tree
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commitdiff
2018-12-13
whitequark
fhdl.ir: implement clock domain propagation.
tree
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commitdiff
2018-12-13
whitequark
fhdl.dsl: use less error-prone Switch/Case two-level...
tree
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commitdiff
2018-12-12
whitequark
fhdl.ir: fix port threading code.
tree
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commitdiff
2018-12-12
whitequark
fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.
tree
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commitdiff
2018-12-12
whitequark
genlib.cdc.MultiReg: pull in from Migen.
tree
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commitdiff
2018-12-12
whitequark
ClockDomain.{rst→reset}, for consistency with ResetInse...
tree
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commitdiff
2018-12-12
whitequark
Initial commit.
tree
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commitdiff