back.verilog: remove debug code.
[nmigen.git] / examples /
2018-12-13 whitequarkfhdl, back: trace and emit source locations of values.
2018-12-13 whitequarkfhdl.ir: implement clock domain propagation.
2018-12-13 whitequarkfhdl.dsl: use less error-prone Switch/Case two-level...
2018-12-12 whitequarkfhdl.ir: fix port threading code.
2018-12-12 whitequarkfhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.
2018-12-12 whitequarkgenlib.cdc.MultiReg: pull in from Migen.
2018-12-12 whitequarkClockDomain.{rst→reset}, for consistency with ResetInse...
2018-12-12 whitequarkInitial commit.