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attempt better grid alignment for fake cells
[soclayout.git]
/
experiments10_verilog
/
2021-04-24
Luke Kenneth Casso...
cleanup mksyms.sh to include FreePDK_C4M45
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commitdiff
2021-04-24
Luke Kenneth Casso...
correct relative link to FreePDK45_c4m45, use submodule
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commitdiff
2021-04-24
Jean-Paul Chaput
Merge branch 'master' of ssh://libre-riscv.org:922...
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commitdiff
2021-04-24
Jean-Paul Chaput
Correct settings for experiment10_verilog & FreePDK45.
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commitdiff
2021-04-19
Staf Verhaegen
experiments10_verilog/freepdk_c4m45: Add link for add.py.
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commitdiff
2021-04-19
Luke Kenneth Casso...
add SPBlock512 instance generator
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commitdiff
2021-04-19
Luke Kenneth Casso...
code-comments
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commitdiff
2021-04-19
Luke Kenneth Casso...
add two SRAMs, document how to do more
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commitdiff
2021-04-14
Luke Kenneth Casso...
add an SRAM and wishbone to add test (makes it bigger)
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commitdiff
2021-04-14
Luke Kenneth Casso...
connect up boundary scan to inputs/outputs
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commitdiff
2021-04-13
Luke Kenneth Casso...
use METAL10 for topRoutingLayer
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commitdiff
2021-04-13
Luke Kenneth Casso...
whoops forgot settings.py
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commitdiff
2021-04-12
Luke Kenneth Casso...
set routingGauge manually
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commitdiff
2021-04-12
Luke Kenneth Casso...
enable HFNS in adder
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commitdiff
2021-04-12
Luke Kenneth Casso...
include (but do not use) FreePDK45 in experiments10
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commitdiff
2021-04-12
Luke Kenneth Casso...
different FreePDK45 experiments10 chip size
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commitdiff
2021-04-12
Luke Kenneth Casso...
experimentation to get experiment10_verilog work with...
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commitdiff
2021-04-12
Luke Kenneth Casso...
add FreePDK45 experiments10_verilog doDesign.py
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commitdiff
2021-04-12
Luke Kenneth Casso...
add FreePDK45 variant of experiments10_verilog
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commitdiff
2021-04-12
Luke Kenneth Casso...
rename sys_clk in adder test experiments10_verilog...
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commitdiff
2021-04-12
Luke Kenneth Casso...
rename JTAG port in adder test experiments10_verilog...
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commitdiff
2021-04-12
Luke Kenneth Casso...
back to "working" verilog add
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commitdiff
2021-04-09
Luke Kenneth Casso...
sigh, broken experiment10_verilog
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commitdiff
2021-04-09
Luke Kenneth Casso...
whitespace cleanup
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commitdiff
2021-04-09
Luke Kenneth Casso...
pad name starts with p_
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commitdiff
2021-04-09
Luke Kenneth Casso...
rename design of experiments10 to match ls180 chip...
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commitdiff
2021-04-02
Luke Kenneth Casso...
experiment with nmigen verilog generation
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