arty/nexys: Rework reset with litedram
[microwatt.git] / fpga / main_bram.vhdl
2020-01-11 Anton BlanchardMerge pull request #133 from antonblanchard/ghdl-synth
2020-01-11 Anton BlanchardFix some ghdlsynth issues with fpga_bram
2019-11-15 Anton BlanchardMerge pull request #118 from antonblanchard/bus-pipeline
2019-10-30 Benjamin Herrenschmidtram: Rework main RAM interface