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divider: Do absolute-value ops in divider instead of decode
[microwatt.git]
/
fpga
/
2019-09-24
Anton Blanchard
Merge pull request #73 from antonblanchard/remove-divid...
tree
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commitdiff
2019-09-24
Anton Blanchard
Remove gcc software divide patch
tree
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commitdiff
2019-09-12
Anton Blanchard
Merge pull request #49 from antonblanchard/icache-2
tree
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commitdiff
2019-09-12
Anton Blanchard
SOC memory wishbone should clear ACK regardless of STB
tree
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commitdiff
2019-09-12
Anton Blanchard
Merge pull request #48 from antonblanchard/clk_gen_bypass
tree
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commitdiff
2019-09-12
Anton Blanchard
Fix clk_gen_bypass
tree
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commitdiff
2019-09-11
Anton Blanchard
Merge pull request #47 from antonblanchard/if-fix
tree
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commitdiff
2019-09-11
Anton Blanchard
Merge pull request #46 from antonblanchard/record-fix
tree
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commitdiff
2019-09-11
Anton Blanchard
Remove names from end record statements
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commitdiff
2019-09-10
Benjamin Herrenschmidt
Share soc.vhdl between FPGA and sim
tree
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commitdiff
2019-09-10
Benjamin Herrenschmidt
Pass wishbone record to bram memory module
tree
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commitdiff
2019-09-10
Benjamin Herrenschmidt
Rework wishbone slave address decoding
tree
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commitdiff
2019-09-10
Benjamin Herrenschmidt
Move wishbone arbiter out of the core
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commitdiff
2019-09-10
Benjamin Herrenschmidt
Re-indent and reformat soc.vhdl
tree
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commitdiff
2019-09-10
Benjamin Herrenschmidt
Split FPGA toplevel from soc
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commitdiff
2019-09-08
Anton Blanchard
Merge pull request #19 from antonblanchard/cmod-a7
tree
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commitdiff
2019-09-08
Anton Blanchard
Cmod A7-35 support
tree
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commitdiff
2019-09-08
Anton Blanchard
Merge pull request #20 from antonblanchard/reset-rework2
tree
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commitdiff
2019-09-08
Anton Blanchard
Merge pull request #21 from antonblanchard/xdc-update
tree
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commitdiff
2019-09-07
Anton Blanchard
Add CONFIG_VOLTAGE and CFGBVS entries
tree
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commitdiff
2019-09-07
Anton Blanchard
Rework SOC reset
tree
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commitdiff
2019-09-07
Anton Blanchard
Rename a few reset signals
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commitdiff
2019-08-29
Anton Blanchard
Merge pull request #10 from antonblanchard/arty-fix
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commitdiff
2019-08-29
Anton Blanchard
Arty A7 reset pin is C2
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commitdiff
2019-08-29
Anton Blanchard
Merge pull request #7 from riktw/fusesoc_arty_a7
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commitdiff
2019-08-29
riktw
Added support for building for Arty A7 boards
tree
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commitdiff
2019-08-28
Anton Blanchard
Merge pull request #5 from antonblanchard/travis-test
tree
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commitdiff
2019-08-27
Anton Blanchard
Fix ghdl build error with pp_soc_memory
tree
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commitdiff
2019-08-27
Anton Blanchard
micropython only requires 512kB of BRAM
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commitdiff
2019-08-26
Anton Blanchard
Rebuild hello world assuming a 50MHz clock
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commitdiff
2019-08-26
Anton Blanchard
Merge pull request #3 from olofk/plle2
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commitdiff
2019-08-26
Olof Kindgren
Add and use plle2 primitive for nexys boards
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commitdiff
2019-08-23
Anton Blanchard
Add a simple hello_world example that also echos input
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commitdiff
2019-08-23
Anton Blanchard
Merge pull request #2 from olofk/fusesoc_nexys_a7
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commitdiff
2019-08-23
Olof Kindgren
Add constraint file for Nexys A7
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commitdiff
2019-08-23
Olof Kindgren
Expose ram init file and memory size through toplevel
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commitdiff
2019-08-23
Olof Kindgren
Add dummy clock generator
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commitdiff
2019-08-23
Anton Blanchard
Add a few more FPGA related files
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commitdiff
2019-08-22
Anton Blanchard
Initial import of microwatt
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commitdiff