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dmi_dtm_ecp5: Use ECP5 JTAGG for DMI
[microwatt.git]
/
fpga
/
2020-05-19
Anton Blanchard
Merge pull request #174 from antonblanchard/yosys-fixes
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commitdiff
2020-05-19
Anton Blanchard
Some yosys fixes
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commitdiff
2020-05-16
Benjamin Herrenschmidt
arty/nexys: Rework reset with litedram
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commitdiff
2020-05-16
Benjamin Herrenschmidt
soc_reset: Use counters, add synchronizers
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commitdiff
2020-05-16
Benjamin Herrenschmidt
litedram: Update to new LiteX/LiteDRAM version
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commitdiff
2020-05-15
Benjamin Herrenschmidt
pp_soc_uart: Fix rx synchronizers and ensure stable...
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commitdiff
2020-05-15
Benjamin Herrenschmidt
pp_fifo: Fix full fifo losing all data on simultaneous...
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commitdiff
2020-05-14
Paul Mackerras
Merge branch 'mmu'
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commitdiff
2020-05-14
Anton Blanchard
Merge pull request #170 from antonblanchard/litedram
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commitdiff
2020-05-08
Benjamin Herrenschmidt
hello_world: Use new headers and frequency from syscon
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commitdiff
2020-05-08
Benjamin Herrenschmidt
syscon: Add syscon registers
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commitdiff
2020-05-08
Benjamin Herrenschmidt
fpga: Hookup nexys-video to litedram
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commitdiff
2020-05-08
Benjamin Herrenschmidt
fpga: Hookup Arty to litedram
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commitdiff
2020-05-08
Benjamin Herrenschmidt
soc: Add DRAM address decoding
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commitdiff
2020-05-08
Benjamin Herrenschmidt
Update hello_world for 100Mhz clock
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commitdiff
2020-01-21
Anton Blanchard
Merge pull request #134 from paulusmack/master
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commitdiff
2020-01-19
Anton Blanchard
Merge pull request #136 from antonblanchard/uart-rx...
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commitdiff
2020-01-19
Anton Blanchard
Add a few FFs on the RX input to avoid metastability...
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commitdiff
2020-01-19
Anton Blanchard
Merge pull request #139 from antonblanchard/reduce-mem
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commitdiff
2020-01-19
Anton Blanchard
Reduce simulated and default FPGA RAM to 384kB
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commitdiff
2020-01-11
Anton Blanchard
Merge pull request #133 from antonblanchard/ghdl-synth
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commitdiff
2020-01-11
Anton Blanchard
Fix some ghdlsynth issues with fpga_bram
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commitdiff
2019-12-09
Anton Blanchard
Merge pull request #122 from paulusmack/benh-sprs
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commitdiff
2019-12-09
Anton Blanchard
Merge pull request #123 from antonblanchard/spi-conf
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commitdiff
2019-12-09
Anton Blanchard
Add SPI configuration to Xilinx constraint files
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commitdiff
2019-11-15
Anton Blanchard
Merge pull request #118 from antonblanchard/bus-pipeline
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commitdiff
2019-10-30
Benjamin Herrenschmidt
ram: Rework main RAM interface
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commitdiff
2019-10-30
Benjamin Herrenschmidt
ram: Add block RAM pipelining
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commitdiff
2019-10-30
Benjamin Herrenschmidt
Add option to not flatten hierarchy
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commitdiff
2019-10-30
Benjamin Herrenschmidt
fpga/bram: Generate stall signal
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commitdiff
2019-10-30
Benjamin Herrenschmidt
pp_uart: reformat
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commitdiff
2019-10-13
Anton Blanchard
Merge pull request #96 from antonblanchard/clk_gen_bypa...
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commitdiff
2019-10-13
Anton Blanchard
Fix clk_gen_bypass
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commitdiff
2019-10-13
Anton Blanchard
Merge pull request #94 from antonblanchard/icbi-nop
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commitdiff
2019-10-13
Anton Blanchard
Merge pull request #93 from antonblanchard/fifo-fix
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commitdiff
2019-10-13
Anton Blanchard
fifo: Reformat
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commitdiff
2019-10-13
Anton Blanchard
fifo: Remove shared variable
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commitdiff
2019-09-30
Anton Blanchard
Merge pull request #77 from antonblanchard/timing
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commitdiff
2019-09-30
Anton Blanchard
Merge pull request #76 from antonblanchard/misc
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commitdiff
2019-09-30
Benjamin Herrenschmidt
Improve PLL/MMCM clocks configuration
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commitdiff
2019-09-30
Benjamin Herrenschmidt
fpga: Arty A7's don't need multiple filesets
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commitdiff
2019-09-30
Benjamin Herrenschmidt
Fix PLL reset signal name in toplevel
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commitdiff
2019-09-24
Anton Blanchard
Merge pull request #73 from antonblanchard/remove-divid...
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commitdiff
2019-09-24
Anton Blanchard
Remove gcc software divide patch
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commitdiff
2019-09-12
Anton Blanchard
Merge pull request #49 from antonblanchard/icache-2
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commitdiff
2019-09-12
Anton Blanchard
SOC memory wishbone should clear ACK regardless of STB
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commitdiff
2019-09-12
Anton Blanchard
Merge pull request #48 from antonblanchard/clk_gen_bypass
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commitdiff
2019-09-12
Anton Blanchard
Fix clk_gen_bypass
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commitdiff
2019-09-11
Anton Blanchard
Merge pull request #47 from antonblanchard/if-fix
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commitdiff
2019-09-11
Anton Blanchard
Merge pull request #46 from antonblanchard/record-fix
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commitdiff
2019-09-11
Anton Blanchard
Remove names from end record statements
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commitdiff
2019-09-10
Benjamin Herrenschmidt
Share soc.vhdl between FPGA and sim
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commitdiff
2019-09-10
Benjamin Herrenschmidt
Pass wishbone record to bram memory module
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commitdiff
2019-09-10
Benjamin Herrenschmidt
Rework wishbone slave address decoding
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commitdiff
2019-09-10
Benjamin Herrenschmidt
Move wishbone arbiter out of the core
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commitdiff
2019-09-10
Benjamin Herrenschmidt
Re-indent and reformat soc.vhdl
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commitdiff
2019-09-10
Benjamin Herrenschmidt
Split FPGA toplevel from soc
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commitdiff
2019-09-08
Anton Blanchard
Merge pull request #19 from antonblanchard/cmod-a7
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commitdiff
2019-09-08
Anton Blanchard
Cmod A7-35 support
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commitdiff
2019-09-08
Anton Blanchard
Merge pull request #20 from antonblanchard/reset-rework2
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commitdiff
2019-09-08
Anton Blanchard
Merge pull request #21 from antonblanchard/xdc-update
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commitdiff
2019-09-07
Anton Blanchard
Add CONFIG_VOLTAGE and CFGBVS entries
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commitdiff
2019-09-07
Anton Blanchard
Rework SOC reset
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commitdiff
2019-09-07
Anton Blanchard
Rename a few reset signals
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commitdiff
2019-08-29
Anton Blanchard
Merge pull request #10 from antonblanchard/arty-fix
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commitdiff
2019-08-29
Anton Blanchard
Arty A7 reset pin is C2
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commitdiff
2019-08-29
Anton Blanchard
Merge pull request #7 from riktw/fusesoc_arty_a7
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commitdiff
2019-08-29
riktw
Added support for building for Arty A7 boards
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commitdiff
2019-08-28
Anton Blanchard
Merge pull request #5 from antonblanchard/travis-test
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commitdiff
2019-08-27
Anton Blanchard
Fix ghdl build error with pp_soc_memory
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commitdiff
2019-08-27
Anton Blanchard
micropython only requires 512kB of BRAM
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commitdiff
2019-08-26
Anton Blanchard
Rebuild hello world assuming a 50MHz clock
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commitdiff
2019-08-26
Anton Blanchard
Merge pull request #3 from olofk/plle2
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commitdiff
2019-08-26
Olof Kindgren
Add and use plle2 primitive for nexys boards
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commitdiff
2019-08-23
Anton Blanchard
Add a simple hello_world example that also echos input
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commitdiff
2019-08-23
Anton Blanchard
Merge pull request #2 from olofk/fusesoc_nexys_a7
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commitdiff
2019-08-23
Olof Kindgren
Add constraint file for Nexys A7
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commitdiff
2019-08-23
Olof Kindgren
Expose ram init file and memory size through toplevel
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commitdiff
2019-08-23
Olof Kindgren
Add dummy clock generator
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commitdiff
2019-08-23
Anton Blanchard
Add a few more FPGA related files
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commitdiff
2019-08-22
Anton Blanchard
Initial import of microwatt
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commitdiff