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[microwatt.git] / fpga /
2019-09-30 Anton BlanchardMerge pull request #77 from antonblanchard/timing tree | commitdiff
2019-09-30 Anton BlanchardMerge pull request #76 from antonblanchard/misc tree | commitdiff
2019-09-30 Benjamin HerrenschmidtImprove PLL/MMCM clocks configuration tree | commitdiff
2019-09-30 Benjamin Herrenschmidtfpga: Arty A7's don't need multiple filesets tree | commitdiff
2019-09-30 Benjamin HerrenschmidtFix PLL reset signal name in toplevel tree | commitdiff
2019-09-24 Anton BlanchardMerge pull request #73 from antonblanchard/remove-divid... tree | commitdiff
2019-09-24 Anton BlanchardRemove gcc software divide patch tree | commitdiff
2019-09-12 Anton BlanchardMerge pull request #49 from antonblanchard/icache-2 tree | commitdiff
2019-09-12 Anton BlanchardSOC memory wishbone should clear ACK regardless of STB tree | commitdiff
2019-09-12 Anton BlanchardMerge pull request #48 from antonblanchard/clk_gen_bypass tree | commitdiff
2019-09-12 Anton BlanchardFix clk_gen_bypass tree | commitdiff
2019-09-11 Anton BlanchardMerge pull request #47 from antonblanchard/if-fix tree | commitdiff
2019-09-11 Anton BlanchardMerge pull request #46 from antonblanchard/record-fix tree | commitdiff
2019-09-11 Anton BlanchardRemove names from end record statements tree | commitdiff
2019-09-10 Benjamin HerrenschmidtShare soc.vhdl between FPGA and sim tree | commitdiff
2019-09-10 Benjamin HerrenschmidtPass wishbone record to bram memory module tree | commitdiff
2019-09-10 Benjamin HerrenschmidtRework wishbone slave address decoding tree | commitdiff
2019-09-10 Benjamin HerrenschmidtMove wishbone arbiter out of the core tree | commitdiff
2019-09-10 Benjamin HerrenschmidtRe-indent and reformat soc.vhdl tree | commitdiff
2019-09-10 Benjamin HerrenschmidtSplit FPGA toplevel from soc tree | commitdiff
2019-09-08 Anton BlanchardMerge pull request #19 from antonblanchard/cmod-a7 tree | commitdiff
2019-09-08 Anton BlanchardCmod A7-35 support tree | commitdiff
2019-09-08 Anton BlanchardMerge pull request #20 from antonblanchard/reset-rework2 tree | commitdiff
2019-09-08 Anton BlanchardMerge pull request #21 from antonblanchard/xdc-update tree | commitdiff
2019-09-07 Anton BlanchardAdd CONFIG_VOLTAGE and CFGBVS entries tree | commitdiff
2019-09-07 Anton BlanchardRework SOC reset tree | commitdiff
2019-09-07 Anton BlanchardRename a few reset signals tree | commitdiff
2019-08-29 Anton BlanchardMerge pull request #10 from antonblanchard/arty-fix tree | commitdiff
2019-08-29 Anton BlanchardArty A7 reset pin is C2 tree | commitdiff
2019-08-29 Anton BlanchardMerge pull request #7 from riktw/fusesoc_arty_a7 tree | commitdiff
2019-08-29 riktwAdded support for building for Arty A7 boards tree | commitdiff
2019-08-28 Anton BlanchardMerge pull request #5 from antonblanchard/travis-test tree | commitdiff
2019-08-27 Anton BlanchardFix ghdl build error with pp_soc_memory tree | commitdiff
2019-08-27 Anton Blanchardmicropython only requires 512kB of BRAM tree | commitdiff
2019-08-26 Anton BlanchardRebuild hello world assuming a 50MHz clock tree | commitdiff
2019-08-26 Anton BlanchardMerge pull request #3 from olofk/plle2 tree | commitdiff
2019-08-26 Olof KindgrenAdd and use plle2 primitive for nexys boards tree | commitdiff
2019-08-23 Anton BlanchardAdd a simple hello_world example that also echos input tree | commitdiff
2019-08-23 Anton BlanchardMerge pull request #2 from olofk/fusesoc_nexys_a7 tree | commitdiff
2019-08-23 Olof KindgrenAdd constraint file for Nexys A7 tree | commitdiff
2019-08-23 Olof KindgrenExpose ram init file and memory size through toplevel tree | commitdiff
2019-08-23 Olof KindgrenAdd dummy clock generator tree | commitdiff
2019-08-23 Anton BlanchardAdd a few more FPGA related files tree | commitdiff
2019-08-22 Anton BlanchardInitial import of microwatt tree | commitdiff