Cover __APPLE__ too for little to big endian
[yosys.git] / frontends / aiger /
2019-04-10 Eddie HungMerge branch 'xaig' into xc7mux
2019-04-10 Eddie Hungparse_aiger() to rename all $lut cells after "clean"
2019-04-08 Eddie HungFix spacing
2019-04-08 Eddie HungMerge branch 'master' into xaig
2019-04-01 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2019-03-19 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-19 Eddie HungMerge pull request #808 from eddiehung/read_aiger
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-03-19 Eddie HungAdd author name
2019-02-26 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-02-26 Eddie Hungparse_xaiger() to really pass single and multi-bit...
2019-02-26 Eddie Hungparse_xaiger() to cope with multi bit inouts
2019-02-26 Eddie Hungparse_xaiger() to untransform $inout.out output ports
2019-02-25 Eddie Hungread_aiger to accept empty string for clk_name, passabl...
2019-02-22 Eddie Hungread_aiger to work with symbol table
2019-02-21 Eddie HungAdd attribution
2019-02-21 Eddie HungMerge branch 'read_aiger' into xaig
2019-02-21 Eddie HungMerge branch 'read_aiger' of https://github.com/eddiehu...
2019-02-21 Eddie HungMerge branch 'read_aiger' into xaig
2019-02-21 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-02-21 Eddie HungMerge branch 'clifford/dffsrfix' of https://github...
2019-02-21 Eddie Hungread_aiger to not do -purge for clean
2019-02-21 Eddie Hunglut/not/and suffix to be ${lut,not,and}
2019-02-21 Eddie Hungread_aiger to also rename 0 index lut when wideports
2019-02-20 Eddie Hungread_aiger: new naming fixes
2019-02-20 Eddie Hungread_aiger to name wires with internal name, less likel...
2019-02-19 Eddie HungSame for ascii AIGERs too
2019-02-19 Eddie Hungread_aiger to cope with non-unique POs
2019-02-19 Eddie HungMerge branch 'master' into xaig
2019-02-19 Eddie HungMerge branch 'master' into read_aiger
2019-02-19 Eddie HungMerge branch 'master' into read_aiger
2019-02-19 Eddie Hungread_aiger to create sane $lut names, and rename when...
2019-02-19 Eddie HungAdd comment
2019-02-19 Eddie HungGet rid of boost dep, fix the FIXMEs for Win32?
2019-02-19 Eddie HungFix for using POSIX basename
2019-02-18 Eddie HungMissing OSX headers?
2019-02-18 Eddie HungMerge branch 'dff_init' into read_aiger
2019-02-17 Eddie Hungread_aiger to ignore line after ands for ascii, not...
2019-02-17 Eddie HungMerge branch 'dff_init' into read_aiger
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-02-17 Eddie HungIn read_xaiger, do not construct ConstEval for every LUT
2019-02-17 Eddie Hungread_aiger to ignore output = input of same wire; also...
2019-02-16 Eddie Hungread_aiger to disable log_debug
2019-02-16 Eddie Hungread_xaiger() to use f.read() not readsome()
2019-02-16 Eddie Hungread_aiger() to cope with constant outputs, mixed widep...
2019-02-15 Eddie Hungread_aiger with more asserts, and call clean
2019-02-14 Eddie HungLeave FIXME for clean
2019-02-14 Eddie HungUse module->addLut()
2019-02-14 Eddie HungUse ConstEval to compute LUT masks
2019-02-13 Eddie HungMerge remote-tracking branch 'origin/read_aiger' into...
2019-02-13 Eddie HungMerge https://github.com/YosysHQ/yosys into xaig
2019-02-12 Eddie HungAdd support for read_aiger -wideports
2019-02-12 Eddie HungAdd support for read_aiger -map
2019-02-12 Eddie HungParse 'm' in xaiger
2019-02-12 Eddie HungMerge branch 'read_aiger' of github.com:eddiehung/yosys...
2019-02-12 Eddie HungUse module->add{Not,And}Gate() functions
2019-02-11 Eddie HungAdd read_xaiger
2019-02-11 Eddie HungDo not break for constraints
2019-02-11 Eddie HungNo increment line_count for binary ANDs
2019-02-11 Eddie HungDo not ignore newline after AND in binary AIG
2019-02-08 Eddie HungMerge remote-tracking branch 'origin/dff_init' into...
2019-02-08 Eddie HungaddDff -> addDffGate as per @daveshah1
2019-02-08 Eddie HungFix tabulation
2019-02-08 Eddie Hung-module_name arg to go before -clk_name
2019-02-08 Eddie HungAllow module name to be determined by argument too
2019-02-08 Eddie HungRefactor into AigerReader class
2019-02-08 Eddie HungParse binary AIG files
2019-02-08 Eddie HungRefactor to parse_aiger_header()
2019-02-08 Eddie HungAdd comment
2019-02-08 Eddie HungHandle reset logic in latches
2019-02-08 Eddie HungChange literal vars from int to unsigned
2019-02-08 Eddie HungCreate clk outside of latch loop
2019-02-08 Eddie HungHandle latch symbols too
2019-02-08 Eddie HungRemove return after log_error
2019-02-08 Eddie HungAdd support for symbol tables
2019-02-08 Eddie HungStub for binary AIGER
2019-02-06 Eddie HungRefactor
2019-02-06 Eddie HungMerge branch 'dff_init' of https://github.com/eddiehung...
2019-02-06 Eddie HungWIP