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Improve write_verilog specify support
[yosys.git]
/
frontends
/
ast
/
ast.cc
2019-05-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into cliff...
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2019-04-30
Benedikt Tutzer
Merge branch 'master' of https://github.com/YosysHQ...
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2019-04-23
Clifford Wolf
Add $specrule cells for $setup/$hold/$skew specify...
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2019-04-23
Clifford Wolf
Allow $specify[23] cells in blackbox modules
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2019-04-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-04-22
Clifford Wolf
Merge pull request #905 from christian-krieg/feature...
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2019-04-22
Clifford Wolf
Merge pull request #941 from Wren6991/sim_lib_io_clke
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2019-04-22
Clifford Wolf
Merge branch 'master' of https://github.com/dh73/yosys_...
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2019-04-22
Clifford Wolf
Merge pull request #916 from YosysHQ/map_cells_before_m...
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2019-04-22
Clifford Wolf
Merge pull request #911 from mmicko/gowin-nobram
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2019-04-22
Clifford Wolf
Merge pull request #909 from zachjs/master
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2019-04-22
Clifford Wolf
Merge pull request #944 from YosysHQ/clifford/pmux2shiftx
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2019-04-22
Clifford Wolf
Merge pull request #945 from YosysHQ/clifford/libwb
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2019-04-21
Eddie Hung
Merge branch 'master' into map_cells_before_map_luts
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2019-04-21
Clifford Wolf
Add "noblackbox" attribute
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2019-04-21
Eddie Hung
Merge remote-tracking branch 'origin/clifford/pmux2shif...
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2019-04-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-04-20
Clifford Wolf
New behavior for front-end handling of whiteboxes
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2019-04-20
Clifford Wolf
Merge pull request #943 from YosysHQ/clifford/whitebox
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2019-04-18
Clifford Wolf
Add "whitebox" attribute, add "read_verilog -wb"
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2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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2019-03-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-21
Clifford Wolf
Improve "read_verilog -dump_vlog[12]" handling of upto...
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2019-03-21
Clifford Wolf
Improve read_verilog debug output capabilities
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2019-01-02
Clifford Wolf
Merge pull request #770 from whitequark/opt_expr_cmp
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2019-01-02
Clifford Wolf
Merge pull request #755 from Icenowy/anlogic-dram-init
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2019-01-02
Clifford Wolf
Merge pull request #750 from Icenowy/anlogic-ff-init
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2019-01-02
Clifford Wolf
Merge pull request #773 from whitequark/opt_lut_elim_fixes
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2019-01-02
Clifford Wolf
Merge pull request #772 from whitequark/synth_lut
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2019-01-02
Clifford Wolf
Merge pull request #771 from whitequark/techmap_cmp2lut
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2019-01-02
Clifford Wolf
Merge pull request #769 from whitequark/typos
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2019-01-02
whitequark
Fix typographical and grammatical errors and inconsiste...
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2018-12-01
Clifford Wolf
Merge pull request #676 from rafaeltp/master
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2018-11-12
Clifford Wolf
Merge pull request #695 from daveshah1/ecp5_bb
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2018-11-04
Clifford Wolf
Various indenting fixes in AST front-end (mostly space...
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2018-10-25
Clifford Wolf
Merge pull request #679 from udif/pr_syntax_error
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2018-10-23
Clifford Wolf
Merge pull request #677 from daveshah1/ecp5_dsp
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2018-10-21
rafaeltp
Merge pull request #1 from YosysHQ/master
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2018-10-20
Clifford Wolf
Merge pull request #674 from rubund/feature/svinterface...
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2018-10-20
Ruben Undheim
Refactor code to avoid code duplication + added comments
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2018-10-20
Ruben Undheim
Support for SystemVerilog interfaces as a port in the...
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2018-10-20
Ruben Undheim
Fixed memory leak
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2018-10-19
Clifford Wolf
Merge pull request #672 from daveshah1/fix_bram
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2018-10-18
Clifford Wolf
Merge pull request #659 from rubund/sv_interfaces
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2018-10-13
Ruben Undheim
Documentation improvements etc.
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2018-10-12
Ruben Undheim
Fix build error with clang
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2018-10-12
Ruben Undheim
Support for 'modports' for System Verilog interfaces
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2018-10-12
Ruben Undheim
Synthesis support for SystemVerilog interfaces
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2018-10-01
Aman Goel
Merge pull request #4 from YosysHQ/master
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-09-14
Clifford Wolf
Merge pull request #625 from aman-goel/master
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2018-08-27
Jim Lawson
Merge branch 'master' into firrtl+modules+shiftfixes
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2018-08-27
Jim Lawson
Merge pull request #3 from YosysHQ/master
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2018-08-23
Clifford Wolf
Merge pull request #610 from udif/udif_specify_round2
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2018-08-23
Clifford Wolf
Merge pull request #614 from udif/pr_disable_dump_ptr
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2018-08-23
Udi Finkelstein
Added -no_dump_ptr flag for AST dump options in 'read_v...
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2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
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2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
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2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
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2018-08-15
Clifford Wolf
Merge pull request #590 from hzeller/remaining-file...
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2018-08-15
Clifford Wolf
Merge pull request #576 from cr1901/no-resource
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2018-08-15
Clifford Wolf
Merge pull request #592 from japm48/master
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2018-08-15
Clifford Wolf
Merge pull request #513 from udif/pr_reg_wire_error
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2018-08-15
Clifford Wolf
Merge pull request #562 from udif/pr_fix_illegal_port_decl
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2018-07-20
Clifford Wolf
Merge pull request #586 from hzeller/more-sourcepos...
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2018-07-20
Henner Zeller
Convert more log_error() to log_file_error() where...
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2018-06-05
Udi Finkelstein
Modified errors into warnings
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2018-05-04
Clifford Wolf
Merge pull request #537 from mithro/yosys-vpr
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2018-05-03
Clifford Wolf
Replace -ignore_redef with -[no]overwrite
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2018-03-11
Udi Finkelstein
This PR should be the base for discussion, do not merge...
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2018-01-05
Clifford Wolf
Merge pull request #479 from Fatsie/latch_without_data
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2018-01-05
Clifford Wolf
Bugfix in hierarchy handling of blackbox module ports
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2017-10-03
Clifford Wolf
Merge branch 'pr_ast_const_funcs' of https://github...
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2017-09-30
Udi Finkelstein
Turned a few member functions into const, esp. dumpAst...
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2017-02-25
Clifford Wolf
Merge branch 'master' of https://github.com/klammerj...
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2017-02-25
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-02-25
Clifford Wolf
Add $live and $fair cell types, add support for s_event...
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2017-02-24
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2017-02-23
Clifford Wolf
Preserve string parameters
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2017-02-11
Clifford Wolf
Merge branch 'master' of https://github.com/stv0g/yosys...
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2017-02-09
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2017-02-04
Clifford Wolf
Add $cover cell type and SVA cover() support
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2016-11-15
Clifford Wolf
Added support for hierarchical defparams
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2016-11-15
Clifford Wolf
Remember global declarations and defines accross read_v...
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2016-10-22
Clifford Wolf
Added avail params to ilang format, check module params...
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2016-09-06
Clifford Wolf
Avoid creation of bogus initial blocks for assert/assum...
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2016-08-28
Clifford Wolf
Removed $predict again
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2016-08-21
Clifford Wolf
Minor improvements to AstNode::dumpAst() and AstNode...
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2016-07-30
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-07-27
Clifford Wolf
Added "read_verilog -dump_rtlil"
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2016-07-21
Clifford Wolf
After reading the SV spec, using non-standard predict...
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2016-07-13
Clifford Wolf
Added basic support for $expect cells
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-06-19
Clifford Wolf
Merge branch 'sv_packages' of https://github.com/rubund...
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2016-06-18
Ruben Undheim
A few modifications after pull request comments
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2016-06-18
Ruben Undheim
Added support for SystemVerilog packages with localpara...
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2016-05-08
Clifford Wolf
Include <cmath> in yosys.h
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2016-04-23
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-04-21
Clifford Wolf
Added "yosys -D" feature
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