Improve write_verilog specify support
[yosys.git] / frontends / ast / ast.cc
2019-05-03 Eddie HungMerge remote-tracking branch 'origin/master' into cliff...
2019-04-30 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-04-23 Clifford WolfAdd $specrule cells for $setup/$hold/$skew specify...
2019-04-23 Clifford WolfAllow $specify[23] cells in blackbox modules
2019-04-22 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-22 Clifford WolfMerge pull request #905 from christian-krieg/feature...
2019-04-22 Clifford WolfMerge pull request #941 from Wren6991/sim_lib_io_clke
2019-04-22 Clifford WolfMerge branch 'master' of https://github.com/dh73/yosys_...
2019-04-22 Clifford WolfMerge pull request #916 from YosysHQ/map_cells_before_m...
2019-04-22 Clifford WolfMerge pull request #911 from mmicko/gowin-nobram
2019-04-22 Clifford WolfMerge pull request #909 from zachjs/master
2019-04-22 Clifford WolfMerge pull request #944 from YosysHQ/clifford/pmux2shiftx
2019-04-22 Clifford WolfMerge pull request #945 from YosysHQ/clifford/libwb
2019-04-21 Eddie HungMerge branch 'master' into map_cells_before_map_luts
2019-04-21 Clifford WolfAdd "noblackbox" attribute
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/clifford/pmux2shif...
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-20 Clifford WolfNew behavior for front-end handling of whiteboxes
2019-04-20 Clifford WolfMerge pull request #943 from YosysHQ/clifford/whitebox
2019-04-18 Clifford WolfAdd "whitebox" attribute, add "read_verilog -wb"
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2019-03-22 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-21 Clifford WolfImprove "read_verilog -dump_vlog[12]" handling of upto...
2019-03-21 Clifford WolfImprove read_verilog debug output capabilities
2019-01-02 Clifford WolfMerge pull request #770 from whitequark/opt_expr_cmp
2019-01-02 Clifford WolfMerge pull request #755 from Icenowy/anlogic-dram-init
2019-01-02 Clifford WolfMerge pull request #750 from Icenowy/anlogic-ff-init
2019-01-02 Clifford WolfMerge pull request #773 from whitequark/opt_lut_elim_fixes
2019-01-02 Clifford WolfMerge pull request #772 from whitequark/synth_lut
2019-01-02 Clifford WolfMerge pull request #771 from whitequark/techmap_cmp2lut
2019-01-02 Clifford WolfMerge pull request #769 from whitequark/typos
2019-01-02 whitequarkFix typographical and grammatical errors and inconsiste...
2018-12-01 Clifford WolfMerge pull request #676 from rafaeltp/master
2018-11-12 Clifford WolfMerge pull request #695 from daveshah1/ecp5_bb
2018-11-04 Clifford WolfVarious indenting fixes in AST front-end (mostly space...
2018-10-25 Clifford WolfMerge pull request #679 from udif/pr_syntax_error
2018-10-23 Clifford WolfMerge pull request #677 from daveshah1/ecp5_dsp
2018-10-21 rafaeltpMerge pull request #1 from YosysHQ/master
2018-10-20 Clifford WolfMerge pull request #674 from rubund/feature/svinterface...
2018-10-20 Ruben UndheimRefactor code to avoid code duplication + added comments
2018-10-20 Ruben UndheimSupport for SystemVerilog interfaces as a port in the...
2018-10-20 Ruben UndheimFixed memory leak
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram
2018-10-18 Clifford WolfMerge pull request #659 from rubund/sv_interfaces
2018-10-13 Ruben UndheimDocumentation improvements etc.
2018-10-12 Ruben UndheimFix build error with clang
2018-10-12 Ruben UndheimSupport for 'modports' for System Verilog interfaces
2018-10-12 Ruben UndheimSynthesis support for SystemVerilog interfaces
2018-10-01 Aman GoelMerge pull request #4 from YosysHQ/master
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-09-14 Clifford WolfMerge pull request #625 from aman-goel/master
2018-08-27 Jim LawsonMerge branch 'master' into firrtl+modules+shiftfixes
2018-08-27 Jim LawsonMerge pull request #3 from YosysHQ/master
2018-08-23 Clifford WolfMerge pull request #610 from udif/udif_specify_round2
2018-08-23 Clifford WolfMerge pull request #614 from udif/pr_disable_dump_ptr
2018-08-23 Udi FinkelsteinAdded -no_dump_ptr flag for AST dump options in 'read_v...
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-08-15 Clifford WolfMerge pull request #590 from hzeller/remaining-file...
2018-08-15 Clifford WolfMerge pull request #576 from cr1901/no-resource
2018-08-15 Clifford WolfMerge pull request #592 from japm48/master
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error
2018-08-15 Clifford WolfMerge pull request #562 from udif/pr_fix_illegal_port_decl
2018-07-20 Clifford WolfMerge pull request #586 from hzeller/more-sourcepos...
2018-07-20 Henner ZellerConvert more log_error() to log_file_error() where...
2018-06-05 Udi FinkelsteinModified errors into warnings
2018-05-04 Clifford WolfMerge pull request #537 from mithro/yosys-vpr
2018-05-03 Clifford WolfReplace -ignore_redef with -[no]overwrite
2018-03-11 Udi FinkelsteinThis PR should be the base for discussion, do not merge...
2018-01-05 Clifford WolfMerge pull request #479 from Fatsie/latch_without_data
2018-01-05 Clifford WolfBugfix in hierarchy handling of blackbox module ports
2017-10-03 Clifford WolfMerge branch 'pr_ast_const_funcs' of https://github...
2017-09-30 Udi FinkelsteinTurned a few member functions into const, esp. dumpAst...
2017-02-25 Clifford WolfMerge branch 'master' of https://github.com/klammerj...
2017-02-25 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-02-25 Clifford WolfAdd $live and $fair cell types, add support for s_event...
2017-02-24 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-23 Clifford WolfPreserve string parameters
2017-02-11 Clifford WolfMerge branch 'master' of https://github.com/stv0g/yosys...
2017-02-09 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-04 Clifford WolfAdd $cover cell type and SVA cover() support
2016-11-15 Clifford WolfAdded support for hierarchical defparams
2016-11-15 Clifford WolfRemember global declarations and defines accross read_v...
2016-10-22 Clifford WolfAdded avail params to ilang format, check module params...
2016-09-06 Clifford WolfAvoid creation of bogus initial blocks for assert/assum...
2016-08-28 Clifford WolfRemoved $predict again
2016-08-21 Clifford WolfMinor improvements to AstNode::dumpAst() and AstNode...
2016-07-30 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-07-27 Clifford WolfAdded "read_verilog -dump_rtlil"
2016-07-21 Clifford WolfAfter reading the SV spec, using non-standard predict...
2016-07-13 Clifford WolfAdded basic support for $expect cells
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-06-19 Clifford WolfMerge branch 'sv_packages' of https://github.com/rubund...
2016-06-18 Ruben UndheimA few modifications after pull request comments
2016-06-18 Ruben UndheimAdded support for SystemVerilog packages with localpara...
2016-05-08 Clifford WolfInclude <cmath> in yosys.h
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfAdded "yosys -D" feature
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