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Avoid creation of bogus initial blocks for assert/assume in always @*
[yosys.git] / frontends / ast / ast.cc
2016-09-06 Clifford WolfAvoid creation of bogus initial blocks for assert/assum... blob | commitdiff | raw
2016-08-28 Clifford WolfRemoved $predict again blob | commitdiff | raw | diff to current
2016-08-21 Clifford WolfMinor improvements to AstNode::dumpAst() and AstNode... blob | commitdiff | raw | diff to current
2016-07-30 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys blob | commitdiff | raw | diff to current
2016-07-27 Clifford WolfAdded "read_verilog -dump_rtlil" blob | commitdiff | raw | diff to current
2016-07-21 Clifford WolfAfter reading the SV spec, using non-standard predict... blob | commitdiff | raw | diff to current
2016-07-13 Clifford WolfAdded basic support for $expect cells blob | commitdiff | raw | diff to current
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com... blob | commitdiff | raw | diff to current
2016-06-19 Clifford WolfMerge branch 'sv_packages' of https://github.com/rubund... blob | commitdiff | raw | diff to current
2016-06-18 Ruben UndheimA few modifications after pull request comments blob | commitdiff | raw | diff to current
2016-06-18 Ruben UndheimAdded support for SystemVerilog packages with localpara... blob | commitdiff | raw | diff to current
2016-05-08 Clifford WolfInclude <cmath> in yosys.h blob | commitdiff | raw | diff to current
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys blob | commitdiff | raw | diff to current
2016-04-21 Clifford WolfAdded "yosys -D" feature blob | commitdiff | raw | diff to current
2016-04-21 Clifford WolfFixed handling of parameters and const functions in... blob | commitdiff | raw | diff to current
2016-02-13 Clifford WolfFixed some visual studio warnings blob | commitdiff | raw | diff to current
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master blob | commitdiff | raw | diff to current
2015-09-25 Clifford WolfFixed segfault in AstNode::asReal blob | commitdiff | raw | diff to current
2015-09-24 Clifford WolfFixed AstNode::mkconst_bits() segfault on zero-sized... blob | commitdiff | raw | diff to current
2015-08-14 Larry DoolittleAnother block of spelling fixes blob | commitdiff | raw | diff to current
2015-07-02 Clifford WolfFixed trailing whitespaces blob | commitdiff | raw | diff to current
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... blob | commitdiff | raw | diff to current
2015-02-26 Clifford WolfAdded non-std verilog assume() statement blob | commitdiff | raw | diff to current
2015-02-14 Clifford WolfAdded "read_verilog -nomeminit" and "nomeminit" attribute blob | commitdiff | raw | diff to current
2015-02-14 Clifford WolfCreating $meminit cells in verilog front-end blob | commitdiff | raw | diff to current
2014-12-29 Clifford WolfAdded global yosys_celltypes blob | commitdiff | raw | diff to current
2014-12-29 Clifford Wolfdict/pool changes in ast blob | commitdiff | raw | diff to current
2014-12-28 Clifford WolfChanged more code to dict<> and pool<> blob | commitdiff | raw | diff to current
2014-12-26 Clifford WolfAdded Yosys::{dict,nodict,vector} container types blob | commitdiff | raw | diff to current
2014-10-25 Clifford WolfFixed constant "cond ? string1 : string2" with strings... blob | commitdiff | raw | diff to current
2014-10-19 Clifford Wolfminor indenting corrections blob | commitdiff | raw | diff to current
2014-10-19 Clifford WolfMerge pull request #40 from parvizp/compile_mac_10.9.2 blob | commitdiff | raw | diff to current
2014-10-19 Parviz PalangpourBuilds on Mac 10.9.2 with LLVM 3.5. blob | commitdiff | raw | diff to current
2014-10-11 Clifford WolfDo not the 'z' modifier in format string (another win32... blob | commitdiff | raw | diff to current
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... blob | commitdiff | raw | diff to current
2014-08-22 Clifford WolfAdded emscripten (emcc) support to build system and... blob | commitdiff | raw | diff to current
2014-08-21 Clifford WolfAdded AstNode::asInt() blob | commitdiff | raw | diff to current
2014-08-21 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys blob | commitdiff | raw | diff to current
2014-08-21 Clifford WolfAdded Verilog/AST support for DPI functions (dpi_call... blob | commitdiff | raw | diff to current
2014-08-21 Clifford WolfAdded support for global tasks and functions blob | commitdiff | raw | diff to current
2014-08-17 Clifford WolfAdded const folding of AST_CASE to AST simplifier blob | commitdiff | raw | diff to current
2014-08-16 Clifford WolfUse stackmap<> in AST ProcessGenerator blob | commitdiff | raw | diff to current
2014-08-14 Clifford WolfFixed bug in "read_verilog -ignore_redef" blob | commitdiff | raw | diff to current
2014-08-14 Clifford WolfChanged the AST genWidthRTLIL subst interface to use... blob | commitdiff | raw | diff to current
2014-08-14 Clifford WolfAdded module->ports blob | commitdiff | raw | diff to current
2014-08-06 Clifford WolfAdded AST_MULTIRANGE (arrays with more than 1 dimension) blob | commitdiff | raw | diff to current
2014-08-01 Clifford WolfPreparations for RTLIL::IdString redesign: cleanup... blob | commitdiff | raw | diff to current
2014-08-01 Clifford WolfReplaced sha1 implementation blob | commitdiff | raw | diff to current
2014-07-31 Clifford WolfAdded module->design and cell->module, wire->module... blob | commitdiff | raw | diff to current
2014-07-31 Clifford WolfMoved some stuff to kernel/yosys.{h,cc}, using Yosys... blob | commitdiff | raw | diff to current
2014-07-28 Clifford WolfAdded support for "upto" wires to Verilog front- and... blob | commitdiff | raw | diff to current
2014-07-28 Clifford WolfUsing log_assert() instead of assert() blob | commitdiff | raw | diff to current
2014-07-27 Clifford WolfAdded proper Design->addModule interface blob | commitdiff | raw | diff to current
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_ blob | commitdiff | raw | diff to current
2014-06-16 Clifford WolfUse undef (x/z vs. NaN) rules for real values from... blob | commitdiff | raw | diff to current
2014-06-15 Clifford WolfImproved AstNode::realAsConst for large numbers blob | commitdiff | raw | diff to current
2014-06-15 Clifford WolfImproved AstNode::asReal for large integers blob | commitdiff | raw | diff to current
2014-06-14 Clifford Wolfimproved (fixed) conversion of real values to bit vectors blob | commitdiff | raw | diff to current
2014-06-14 Clifford WolfAdded handling of real-valued parameters/localparams blob | commitdiff | raw | diff to current
2014-06-14 Clifford WolfImplemented basic real arithmetic blob | commitdiff | raw | diff to current
2014-06-13 Clifford WolfAdded Verilog lexer and parser support for real values blob | commitdiff | raw | diff to current
2014-06-07 Clifford WolfAdd support for cell arrays blob | commitdiff | raw | diff to current
2014-06-06 Clifford Wolfadded while and repeat support to verilog parser blob | commitdiff | raw | diff to current
2014-03-05 Clifford WolfInclude id2ast pointers when dumping AST blob | commitdiff | raw | diff to current
2014-02-20 Clifford WolfCleanups in handling of read_verilog -defer and -icells blob | commitdiff | raw | diff to current
2014-02-17 Clifford WolfAdded Verilog support for "`default_nettype none" blob | commitdiff | raw | diff to current
2014-02-14 Clifford WolfAdded support for FOR loops in function calls in parameters blob | commitdiff | raw | diff to current
2014-02-14 Clifford WolfCreated basic support for function calls in parameter... blob | commitdiff | raw | diff to current
2014-02-13 Clifford WolfImplemented read_verilog -defer blob | commitdiff | raw | diff to current
2014-02-01 Clifford WolfAdded constant size expression support of sized constants blob | commitdiff | raw | diff to current
2014-01-28 Clifford WolfAdded read_verilog -icells option blob | commitdiff | raw | diff to current
2014-01-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... blob | commitdiff | raw | diff to current
2014-01-20 Clifford WolfFixed algorithmic complexity of AST simplification... blob | commitdiff | raw | diff to current
2014-01-20 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... blob | commitdiff | raw | diff to current
2014-01-19 Clifford WolfAdded Verilog parser support for asserts blob | commitdiff | raw | diff to current
2014-01-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... blob | commitdiff | raw | diff to current
2013-12-27 Clifford WolfAdded proper === and !== support in constant expressions blob | commitdiff | raw | diff to current
2013-12-05 Clifford WolfKeep strings as strings in const ternary and concat blob | commitdiff | raw | diff to current
2013-12-05 Clifford WolfAdded AstNode::mkconst_str API blob | commitdiff | raw | diff to current
2013-12-04 Clifford WolfVarious improvements in support for generate statements blob | commitdiff | raw | diff to current
2013-12-04 Clifford WolfReplaced signed_parameters API with CONST_FLAG_SIGNED blob | commitdiff | raw | diff to current
2013-12-04 Clifford WolfReplaced RTLIL::Const::str with generic decoder method blob | commitdiff | raw | diff to current
2013-11-24 Clifford WolfAdded verilog frontend -ignore_redef option blob | commitdiff | raw | diff to current
2013-11-24 Clifford WolfRemove auto_wire framework (smarter than the verilog... blob | commitdiff | raw | diff to current
2013-11-24 Clifford WolfImplemented correct handling of signed module parameters blob | commitdiff | raw | diff to current
2013-11-22 Clifford WolfRenamed "placeholder" to "blackbox" blob | commitdiff | raw | diff to current
2013-11-18 Clifford WolfAdded dumping of attributes in AST frontend blob | commitdiff | raw | diff to current
2013-11-10 Clifford WolfCall internal checker more often blob | commitdiff | raw | diff to current
2013-11-07 Clifford WolfVarious fixes for correct parameter support blob | commitdiff | raw | diff to current
2013-11-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys blob | commitdiff | raw | diff to current
2013-11-02 Clifford WolfVarious ast changes for early expression width detectio... blob | commitdiff | raw | diff to current
2013-10-24 Clifford WolfFixed handling of boolean attributes (frontends) blob | commitdiff | raw | diff to current
2013-08-19 Clifford WolfImproved ast dumping (ast/verilog frontend) blob | commitdiff | raw | diff to current
2013-07-27 Clifford WolfAdded "design" command (-reset, -save, -load) blob | commitdiff | raw | diff to current
2013-07-07 Clifford WolfFixed AST_CONSTANT node generation blob | commitdiff | raw | diff to current
2013-07-04 Clifford WolfAdded defparam support to Verilog/AST frontend blob | commitdiff | raw | diff to current
2013-06-10 Clifford WolfEnabled AST/Verilog front-end optimizations per default blob | commitdiff | raw | diff to current
2013-05-24 Clifford WolfAdded log_assert() api blob | commitdiff | raw | diff to current
2013-05-16 Clifford WolfMerge branch 'bugfix' blob | commitdiff | raw | diff to current
2013-04-26 Clifford WolfFixed handling of positional module parameters blob | commitdiff | raw | diff to current
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