projects / yosys.git / history
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
Added module->design and cell->module, wire->module pointers
[yosys.git] / frontends / ast / ast.cc
2014-07-31 Clifford WolfAdded module->design and cell->module, wire->module... blob | commitdiff | raw
2014-07-31 Clifford WolfMoved some stuff to kernel/yosys.{h,cc}, using Yosys... blob | commitdiff | raw | diff to current
2014-07-28 Clifford WolfAdded support for "upto" wires to Verilog front- and... blob | commitdiff | raw | diff to current
2014-07-28 Clifford WolfUsing log_assert() instead of assert() blob | commitdiff | raw | diff to current
2014-07-27 Clifford WolfAdded proper Design->addModule interface blob | commitdiff | raw | diff to current
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_ blob | commitdiff | raw | diff to current
2014-06-16 Clifford WolfUse undef (x/z vs. NaN) rules for real values from... blob | commitdiff | raw | diff to current
2014-06-15 Clifford WolfImproved AstNode::realAsConst for large numbers blob | commitdiff | raw | diff to current
2014-06-15 Clifford WolfImproved AstNode::asReal for large integers blob | commitdiff | raw | diff to current
2014-06-14 Clifford Wolfimproved (fixed) conversion of real values to bit vectors blob | commitdiff | raw | diff to current
2014-06-14 Clifford WolfAdded handling of real-valued parameters/localparams blob | commitdiff | raw | diff to current
2014-06-14 Clifford WolfImplemented basic real arithmetic blob | commitdiff | raw | diff to current
2014-06-13 Clifford WolfAdded Verilog lexer and parser support for real values blob | commitdiff | raw | diff to current
2014-06-07 Clifford WolfAdd support for cell arrays blob | commitdiff | raw | diff to current
2014-06-06 Clifford Wolfadded while and repeat support to verilog parser blob | commitdiff | raw | diff to current
2014-03-05 Clifford WolfInclude id2ast pointers when dumping AST blob | commitdiff | raw | diff to current
2014-02-20 Clifford WolfCleanups in handling of read_verilog -defer and -icells blob | commitdiff | raw | diff to current
2014-02-17 Clifford WolfAdded Verilog support for "`default_nettype none" blob | commitdiff | raw | diff to current
2014-02-14 Clifford WolfAdded support for FOR loops in function calls in parameters blob | commitdiff | raw | diff to current
2014-02-14 Clifford WolfCreated basic support for function calls in parameter... blob | commitdiff | raw | diff to current
2014-02-13 Clifford WolfImplemented read_verilog -defer blob | commitdiff | raw | diff to current
2014-02-01 Clifford WolfAdded constant size expression support of sized constants blob | commitdiff | raw | diff to current
2014-01-28 Clifford WolfAdded read_verilog -icells option blob | commitdiff | raw | diff to current
2014-01-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... blob | commitdiff | raw | diff to current
2014-01-20 Clifford WolfFixed algorithmic complexity of AST simplification... blob | commitdiff | raw | diff to current
2014-01-20 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... blob | commitdiff | raw | diff to current
2014-01-19 Clifford WolfAdded Verilog parser support for asserts blob | commitdiff | raw | diff to current
2014-01-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... blob | commitdiff | raw | diff to current
2013-12-27 Clifford WolfAdded proper === and !== support in constant expressions blob | commitdiff | raw | diff to current
2013-12-05 Clifford WolfKeep strings as strings in const ternary and concat blob | commitdiff | raw | diff to current
2013-12-05 Clifford WolfAdded AstNode::mkconst_str API blob | commitdiff | raw | diff to current
2013-12-04 Clifford WolfVarious improvements in support for generate statements blob | commitdiff | raw | diff to current
2013-12-04 Clifford WolfReplaced signed_parameters API with CONST_FLAG_SIGNED blob | commitdiff | raw | diff to current
2013-12-04 Clifford WolfReplaced RTLIL::Const::str with generic decoder method blob | commitdiff | raw | diff to current
2013-11-24 Clifford WolfAdded verilog frontend -ignore_redef option blob | commitdiff | raw | diff to current
2013-11-24 Clifford WolfRemove auto_wire framework (smarter than the verilog... blob | commitdiff | raw | diff to current
2013-11-24 Clifford WolfImplemented correct handling of signed module parameters blob | commitdiff | raw | diff to current
2013-11-22 Clifford WolfRenamed "placeholder" to "blackbox" blob | commitdiff | raw | diff to current
2013-11-18 Clifford WolfAdded dumping of attributes in AST frontend blob | commitdiff | raw | diff to current
2013-11-10 Clifford WolfCall internal checker more often blob | commitdiff | raw | diff to current
2013-11-07 Clifford WolfVarious fixes for correct parameter support blob | commitdiff | raw | diff to current
2013-11-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys blob | commitdiff | raw | diff to current
2013-11-02 Clifford WolfVarious ast changes for early expression width detectio... blob | commitdiff | raw | diff to current
2013-10-24 Clifford WolfFixed handling of boolean attributes (frontends) blob | commitdiff | raw | diff to current
2013-08-19 Clifford WolfImproved ast dumping (ast/verilog frontend) blob | commitdiff | raw | diff to current
2013-07-27 Clifford WolfAdded "design" command (-reset, -save, -load) blob | commitdiff | raw | diff to current
2013-07-07 Clifford WolfFixed AST_CONSTANT node generation blob | commitdiff | raw | diff to current
2013-07-04 Clifford WolfAdded defparam support to Verilog/AST frontend blob | commitdiff | raw | diff to current
2013-06-10 Clifford WolfEnabled AST/Verilog front-end optimizations per default blob | commitdiff | raw | diff to current
2013-05-24 Clifford WolfAdded log_assert() api blob | commitdiff | raw | diff to current
2013-05-16 Clifford WolfMerge branch 'bugfix' blob | commitdiff | raw | diff to current
2013-04-26 Clifford WolfFixed handling of positional module parameters blob | commitdiff | raw | diff to current
2013-04-26 Clifford WolfOnly use sha1 checksums for names of parametric modules... blob | commitdiff | raw | diff to current
2013-03-31 Clifford WolfNow only use value from "initial" when no matching... blob | commitdiff | raw | diff to current
2013-03-31 Clifford WolfAdded AST_INITIAL (before verilog "initial" was mapped... blob | commitdiff | raw | diff to current
2013-03-28 Clifford WolfImplemented proper handling of stub placeholder modules blob | commitdiff | raw | diff to current
2013-03-24 Clifford WolfAdded mem2reg option to verilog frontend blob | commitdiff | raw | diff to current
2013-02-27 Clifford WolfMoved stand-alone libs to libs/ directory and added... blob | commitdiff | raw | diff to current
2013-02-26 Clifford WolfAdded support for verilog genblock[index].member syntax blob | commitdiff | raw | diff to current
2013-01-05 Clifford Wolfinitial import blob | commitdiff | raw | diff to current