| 2018-08-15 |
Clifford Wolf | Merge pull request #591 from hzeller/virtual-override |
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| 2018-08-15 |
Clifford Wolf | Merge pull request #590 from hzeller/remaining-file... |
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| 2018-08-15 |
Clifford Wolf | Merge pull request #576 from cr1901/no-resource |
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| 2018-08-15 |
Clifford Wolf | Merge pull request #592 from japm48/master |
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| 2018-08-15 |
Clifford Wolf | Merge pull request #513 from udif/pr_reg_wire_error |
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| 2018-07-21 |
Henner Zeller | Consistent use of 'override' for virtual methods in... |
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| 2018-06-05 |
Udi Finkelstein | Modified errors into warnings |
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| 2018-05-04 |
Clifford Wolf | Merge pull request #537 from mithro/yosys-vpr |
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| 2018-05-03 |
Clifford Wolf | Replace -ignore_redef with -[no]overwrite |
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| 2018-03-11 |
Udi Finkelstein | This PR should be the base for discussion, do not merge... |
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| 2018-01-05 |
Clifford Wolf | Merge pull request #479 from Fatsie/latch_without_data |
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| 2018-01-05 |
Clifford Wolf | Bugfix in hierarchy handling of blackbox module ports |
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| 2017-10-03 |
Clifford Wolf | Merge branch 'pr_ast_const_funcs' of https://github... |
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| 2017-09-30 |
Udi Finkelstein | Turned a few member functions into const, esp. dumpAst... |
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| 2017-02-25 |
Clifford Wolf | Merge branch 'master' of https://github.com/klammerj... |
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| 2017-02-25 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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| 2017-02-25 |
Clifford Wolf | Add $live and $fair cell types, add support for s_event... |
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| 2017-02-11 |
Clifford Wolf | Merge branch 'master' of https://github.com/stv0g/yosys... |
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| 2017-02-09 |
Andrew Zonenberg | Merge https://github.com/cliffordwolf/yosys |
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| 2017-02-04 |
Clifford Wolf | Add $cover cell type and SVA cover() support |
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| 2016-09-06 |
Clifford Wolf | Avoid creation of bogus initial blocks for assert/assum... |
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| 2016-08-28 |
Clifford Wolf | Removed $predict again |
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| 2016-08-21 |
Clifford Wolf | Another bugfix in mem2reg code |
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| 2016-07-30 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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| 2016-07-27 |
Clifford Wolf | Added "read_verilog -dump_rtlil" |
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| 2016-07-21 |
Clifford Wolf | After reading the SV spec, using non-standard predict... |
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| 2016-07-13 |
Clifford Wolf | Added basic support for $expect cells |
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| 2016-07-08 |
Clifford Wolf | Merge branch 'yosys-0.5-vtr' of https://github.com... |
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| 2016-06-19 |
Clifford Wolf | Merge branch 'sv_packages' of https://github.com/rubund... |
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| 2016-06-18 |
Ruben Undheim | Added support for SystemVerilog packages with localpara... |
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| 2016-05-27 |
Clifford Wolf | Fixed access-after-delete bug in mem2reg code |
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| 2016-04-23 |
Andrew Zonenberg | Merge https://github.com/cliffordwolf/yosys |
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| 2016-04-21 |
Clifford Wolf | Fixed handling of parameters and const functions in... |
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| 2015-08-14 |
Clifford Wolf | Spell check (by Larry Doolittle) |
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| 2015-07-31 |
Clifford Wolf | Added WORDS parameter to $meminit |
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| 2015-07-29 |
Clifford Wolf | Fixed nested mem2reg |
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| 2015-07-02 |
Clifford Wolf | Fixed trailing whitespaces |
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| 2015-04-03 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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| 2015-02-26 |
Clifford Wolf | Added non-std verilog assume() statement |
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| 2015-02-14 |
Clifford Wolf | Added "read_verilog -nomeminit" and "nomeminit" attribute |
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| 2015-02-14 |
Clifford Wolf | Creating $meminit cells in verilog front-end |
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| 2014-12-29 |
Clifford Wolf | dict/pool changes in ast |
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| 2014-12-28 |
Clifford Wolf | Changed more code to dict<> and pool<> |
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| 2014-12-26 |
Clifford Wolf | Added Yosys::{dict,nodict,vector} container types |
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| 2014-10-26 |
Clifford Wolf | Added support for $readmemh/$readmemb |
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| 2014-10-15 |
Clifford Wolf | Fixed handling of invalid array access in mem2reg code |
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| 2014-09-22 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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| 2014-08-21 |
Clifford Wolf | Added AstNode::asInt() |
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| 2014-08-21 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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| 2014-08-21 |
Clifford Wolf | Added Verilog/AST support for DPI functions (dpi_call... |
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| 2014-08-17 |
Clifford Wolf | Added const folding of AST_CASE to AST simplifier |
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| 2014-08-16 |
Clifford Wolf | Use stackmap<> in AST ProcessGenerator |
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| 2014-08-14 |
Clifford Wolf | Changed the AST genWidthRTLIL subst interface to use... |
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| 2014-08-06 |
Clifford Wolf | Added AST_MULTIRANGE (arrays with more than 1 dimension) |
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| 2014-08-05 |
Clifford Wolf | Improved scope resolution of local regs in Verilog... |
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| 2014-07-31 |
Clifford Wolf | Moved some stuff to kernel/yosys.{h,cc}, using Yosys... |
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| 2014-07-28 |
Clifford Wolf | Added support for "upto" wires to Verilog front- and... |
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| 2014-06-17 |
Clifford Wolf | Added AstNode::MEM2REG_FL_CMPLX_LHS |
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| 2014-06-16 |
Clifford Wolf | Added found_real feature to AstNode::detectSignWidth |
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| 2014-06-14 |
Clifford Wolf | improved (fixed) conversion of real values to bit vectors |
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| 2014-06-14 |
Clifford Wolf | Implemented basic real arithmetic |
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| 2014-06-13 |
Clifford Wolf | Added Verilog lexer and parser support for real values |
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| 2014-06-07 |
Clifford Wolf | Add support for cell arrays |
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| 2014-06-06 |
Clifford Wolf | further improved const function support |
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| 2014-06-06 |
Clifford Wolf | improved const function support |
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| 2014-06-06 |
Clifford Wolf | added while and repeat support to verilog parser |
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| 2014-02-17 |
Clifford Wolf | Added Verilog support for "`default_nettype none" |
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| 2014-02-14 |
Clifford Wolf | Added support for FOR loops in function calls in parameters |
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| 2014-02-14 |
Clifford Wolf | Created basic support for function calls in parameter... |
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| 2014-02-13 |
Clifford Wolf | Implemented read_verilog -defer |
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| 2014-02-01 |
Clifford Wolf | Added constant size expression support of sized constants |
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| 2014-01-28 |
Clifford Wolf | Added read_verilog -icells option |
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| 2014-01-22 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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| 2014-01-20 |
Clifford Wolf | Fixed algorithmic complexity of AST simplification... |
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| 2014-01-20 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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| 2014-01-19 |
Clifford Wolf | Added Verilog parser support for asserts |
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| 2014-01-03 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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| 2013-12-27 |
Clifford Wolf | Added proper === and !== support in constant expressions |
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| 2013-12-05 |
Clifford Wolf | Keep strings as strings in const ternary and concat |
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| 2013-12-05 |
Clifford Wolf | Added AstNode::mkconst_str API |
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| 2013-12-04 |
Clifford Wolf | Various improvements in support for generate statements |
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| 2013-12-04 |
Clifford Wolf | Replaced signed_parameters API with CONST_FLAG_SIGNED |
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| 2013-12-04 |
Clifford Wolf | Replaced RTLIL::Const::str with generic decoder method |
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| 2013-11-24 |
Clifford Wolf | Added verilog frontend -ignore_redef option |
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| 2013-11-24 |
Clifford Wolf | Remove auto_wire framework (smarter than the verilog... |
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| 2013-11-24 |
Clifford Wolf | Implemented correct handling of signed module parameters |
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| 2013-11-21 |
Clifford Wolf | Major improvements in mem2reg and added "init" sync... |
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| 2013-11-03 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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| 2013-11-02 |
Clifford Wolf | Various ast changes for early expression width detectio... |
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| 2013-10-24 |
Clifford Wolf | Fixed handling of boolean attributes (frontends) |
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| 2013-08-19 |
Clifford Wolf | Improved ast dumping (ast/verilog frontend) |
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| 2013-07-27 |
Clifford Wolf | Added "design" command (-reset, -save, -load) |
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| 2013-07-09 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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| 2013-07-09 |
Clifford Wolf | Major redesign of expr width/sign detecion (verilog... |
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| 2013-07-04 |
Clifford Wolf | Added defparam support to Verilog/AST frontend |
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| 2013-06-10 |
Clifford Wolf | Enabled AST/Verilog front-end optimizations per default |
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| 2013-05-16 |
Clifford Wolf | Merge branch 'bugfix' |
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| 2013-03-31 |
Clifford Wolf | Now only use value from "initial" when no matching... |
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| 2013-03-31 |
Clifford Wolf | Added AST_INITIAL (before verilog "initial" was mapped... |
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| 2013-03-28 |
Clifford Wolf | Implemented proper handling of stub placeholder modules |
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