git.libre-soc.org Git - yosys.git/history

2014-06-06	Clifford Wolf	further improved const function support	blob \| commitdiff \| raw
2014-06-06	Clifford Wolf	improved const function support	blob \| commitdiff \| raw \| diff to current
2014-06-06	Clifford Wolf	added while and repeat support to verilog parser	blob \| commitdiff \| raw \| diff to current
2014-02-17	Clifford Wolf	Added Verilog support for "`default_nettype none"	blob \| commitdiff \| raw \| diff to current
2014-02-14	Clifford Wolf	Added support for FOR loops in function calls in parameters	blob \| commitdiff \| raw \| diff to current
2014-02-14	Clifford Wolf	Created basic support for function calls in parameter...	blob \| commitdiff \| raw \| diff to current
2014-02-13	Clifford Wolf	Implemented read_verilog -defer	blob \| commitdiff \| raw \| diff to current
2014-02-01	Clifford Wolf	Added constant size expression support of sized constants	blob \| commitdiff \| raw \| diff to current
2014-01-28	Clifford Wolf	Added read_verilog -icells option	blob \| commitdiff \| raw \| diff to current
2014-01-22	Ahmed Irfan	Merge branch 'master' of https://github.com/cliffordwol...	blob \| commitdiff \| raw \| diff to current
2014-01-20	Clifford Wolf	Fixed algorithmic complexity of AST simplification...	blob \| commitdiff \| raw \| diff to current
2014-01-20	Ahmed Irfan	Merge branch 'master' of https://github.com/cliffordwol...	blob \| commitdiff \| raw \| diff to current
2014-01-19	Clifford Wolf	Added Verilog parser support for asserts	blob \| commitdiff \| raw \| diff to current
2014-01-03	Ahmed Irfan	Merge branch 'master' of https://github.com/cliffordwol...	blob \| commitdiff \| raw \| diff to current
2013-12-27	Clifford Wolf	Added proper === and !== support in constant expressions	blob \| commitdiff \| raw \| diff to current
2013-12-05	Clifford Wolf	Keep strings as strings in const ternary and concat	blob \| commitdiff \| raw \| diff to current
2013-12-05	Clifford Wolf	Added AstNode::mkconst_str API	blob \| commitdiff \| raw \| diff to current
2013-12-04	Clifford Wolf	Various improvements in support for generate statements	blob \| commitdiff \| raw \| diff to current
2013-12-04	Clifford Wolf	Replaced signed_parameters API with CONST_FLAG_SIGNED	blob \| commitdiff \| raw \| diff to current
2013-12-04	Clifford Wolf	Replaced RTLIL::Const::str with generic decoder method	blob \| commitdiff \| raw \| diff to current
2013-11-24	Clifford Wolf	Added verilog frontend -ignore_redef option	blob \| commitdiff \| raw \| diff to current
2013-11-24	Clifford Wolf	Remove auto_wire framework (smarter than the verilog...	blob \| commitdiff \| raw \| diff to current
2013-11-24	Clifford Wolf	Implemented correct handling of signed module parameters	blob \| commitdiff \| raw \| diff to current
2013-11-21	Clifford Wolf	Major improvements in mem2reg and added "init" sync...	blob \| commitdiff \| raw \| diff to current
2013-11-03	Clifford Wolf	Merge branch 'master' of github.com:cliffordwolf/yosys	blob \| commitdiff \| raw \| diff to current
2013-11-02	Clifford Wolf	Various ast changes for early expression width detectio...	blob \| commitdiff \| raw \| diff to current
2013-10-24	Clifford Wolf	Fixed handling of boolean attributes (frontends)	blob \| commitdiff \| raw \| diff to current
2013-08-19	Clifford Wolf	Improved ast dumping (ast/verilog frontend)	blob \| commitdiff \| raw \| diff to current
2013-07-27	Clifford Wolf	Added "design" command (-reset, -save, -load)	blob \| commitdiff \| raw \| diff to current
2013-07-09	Clifford Wolf	Merge branch 'master' of github.com:cliffordwolf/yosys	blob \| commitdiff \| raw \| diff to current
2013-07-09	Clifford Wolf	Major redesign of expr width/sign detecion (verilog...	blob \| commitdiff \| raw \| diff to current
2013-07-04	Clifford Wolf	Added defparam support to Verilog/AST frontend	blob \| commitdiff \| raw \| diff to current
2013-06-10	Clifford Wolf	Enabled AST/Verilog front-end optimizations per default	blob \| commitdiff \| raw \| diff to current
2013-05-16	Clifford Wolf	Merge branch 'bugfix'	blob \| commitdiff \| raw \| diff to current
2013-03-31	Clifford Wolf	Now only use value from "initial" when no matching...	blob \| commitdiff \| raw \| diff to current
2013-03-31	Clifford Wolf	Added AST_INITIAL (before verilog "initial" was mapped...	blob \| commitdiff \| raw \| diff to current
2013-03-28	Clifford Wolf	Implemented proper handling of stub placeholder modules	blob \| commitdiff \| raw \| diff to current
2013-03-25	Clifford Wolf	Added nosync attribute and some async reset related...	blob \| commitdiff \| raw \| diff to current
2013-03-24	Clifford Wolf	Added mem2reg option to verilog frontend	blob \| commitdiff \| raw \| diff to current
2013-03-24	Clifford Wolf	Improved mem2reg handling in ast simplifier	blob \| commitdiff \| raw \| diff to current
2013-02-26	Clifford Wolf	Added support for verilog genblock[index].member syntax	blob \| commitdiff \| raw \| diff to current
2013-01-05	Clifford Wolf	initial import	blob \| commitdiff \| raw \| diff to current

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