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Creating $meminit cells in verilog front-end
[yosys.git] / frontends / ast / ast.h
2015-02-14 Clifford WolfCreating $meminit cells in verilog front-end blob | commitdiff | raw
2014-12-29 Clifford Wolfdict/pool changes in ast blob | commitdiff | raw | diff to current
2014-12-28 Clifford WolfChanged more code to dict<> and pool<> blob | commitdiff | raw | diff to current
2014-12-26 Clifford WolfAdded Yosys::{dict,nodict,vector} container types blob | commitdiff | raw | diff to current
2014-10-26 Clifford WolfAdded support for $readmemh/$readmemb blob | commitdiff | raw | diff to current
2014-10-15 Clifford WolfFixed handling of invalid array access in mem2reg code blob | commitdiff | raw | diff to current
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... blob | commitdiff | raw | diff to current
2014-08-21 Clifford WolfAdded AstNode::asInt() blob | commitdiff | raw | diff to current
2014-08-21 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys blob | commitdiff | raw | diff to current
2014-08-21 Clifford WolfAdded Verilog/AST support for DPI functions (dpi_call... blob | commitdiff | raw | diff to current
2014-08-17 Clifford WolfAdded const folding of AST_CASE to AST simplifier blob | commitdiff | raw | diff to current
2014-08-16 Clifford WolfUse stackmap<> in AST ProcessGenerator blob | commitdiff | raw | diff to current
2014-08-14 Clifford WolfChanged the AST genWidthRTLIL subst interface to use... blob | commitdiff | raw | diff to current
2014-08-06 Clifford WolfAdded AST_MULTIRANGE (arrays with more than 1 dimension) blob | commitdiff | raw | diff to current
2014-08-05 Clifford WolfImproved scope resolution of local regs in Verilog... blob | commitdiff | raw | diff to current
2014-07-31 Clifford WolfMoved some stuff to kernel/yosys.{h,cc}, using Yosys... blob | commitdiff | raw | diff to current
2014-07-28 Clifford WolfAdded support for "upto" wires to Verilog front- and... blob | commitdiff | raw | diff to current
2014-06-17 Clifford WolfAdded AstNode::MEM2REG_FL_CMPLX_LHS blob | commitdiff | raw | diff to current
2014-06-16 Clifford WolfAdded found_real feature to AstNode::detectSignWidth blob | commitdiff | raw | diff to current
2014-06-14 Clifford Wolfimproved (fixed) conversion of real values to bit vectors blob | commitdiff | raw | diff to current
2014-06-14 Clifford WolfImplemented basic real arithmetic blob | commitdiff | raw | diff to current
2014-06-13 Clifford WolfAdded Verilog lexer and parser support for real values blob | commitdiff | raw | diff to current
2014-06-07 Clifford WolfAdd support for cell arrays blob | commitdiff | raw | diff to current
2014-06-06 Clifford Wolffurther improved const function support blob | commitdiff | raw | diff to current
2014-06-06 Clifford Wolfimproved const function support blob | commitdiff | raw | diff to current
2014-06-06 Clifford Wolfadded while and repeat support to verilog parser blob | commitdiff | raw | diff to current
2014-02-17 Clifford WolfAdded Verilog support for "`default_nettype none" blob | commitdiff | raw | diff to current
2014-02-14 Clifford WolfAdded support for FOR loops in function calls in parameters blob | commitdiff | raw | diff to current
2014-02-14 Clifford WolfCreated basic support for function calls in parameter... blob | commitdiff | raw | diff to current
2014-02-13 Clifford WolfImplemented read_verilog -defer blob | commitdiff | raw | diff to current
2014-02-01 Clifford WolfAdded constant size expression support of sized constants blob | commitdiff | raw | diff to current
2014-01-28 Clifford WolfAdded read_verilog -icells option blob | commitdiff | raw | diff to current
2014-01-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... blob | commitdiff | raw | diff to current
2014-01-20 Clifford WolfFixed algorithmic complexity of AST simplification... blob | commitdiff | raw | diff to current
2014-01-20 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... blob | commitdiff | raw | diff to current
2014-01-19 Clifford WolfAdded Verilog parser support for asserts blob | commitdiff | raw | diff to current
2014-01-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... blob | commitdiff | raw | diff to current
2013-12-27 Clifford WolfAdded proper === and !== support in constant expressions blob | commitdiff | raw | diff to current
2013-12-05 Clifford WolfKeep strings as strings in const ternary and concat blob | commitdiff | raw | diff to current
2013-12-05 Clifford WolfAdded AstNode::mkconst_str API blob | commitdiff | raw | diff to current
2013-12-04 Clifford WolfVarious improvements in support for generate statements blob | commitdiff | raw | diff to current
2013-12-04 Clifford WolfReplaced signed_parameters API with CONST_FLAG_SIGNED blob | commitdiff | raw | diff to current
2013-12-04 Clifford WolfReplaced RTLIL::Const::str with generic decoder method blob | commitdiff | raw | diff to current
2013-11-24 Clifford WolfAdded verilog frontend -ignore_redef option blob | commitdiff | raw | diff to current
2013-11-24 Clifford WolfRemove auto_wire framework (smarter than the verilog... blob | commitdiff | raw | diff to current
2013-11-24 Clifford WolfImplemented correct handling of signed module parameters blob | commitdiff | raw | diff to current
2013-11-21 Clifford WolfMajor improvements in mem2reg and added "init" sync... blob | commitdiff | raw | diff to current
2013-11-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys blob | commitdiff | raw | diff to current
2013-11-02 Clifford WolfVarious ast changes for early expression width detectio... blob | commitdiff | raw | diff to current
2013-10-24 Clifford WolfFixed handling of boolean attributes (frontends) blob | commitdiff | raw | diff to current
2013-08-19 Clifford WolfImproved ast dumping (ast/verilog frontend) blob | commitdiff | raw | diff to current
2013-07-27 Clifford WolfAdded "design" command (-reset, -save, -load) blob | commitdiff | raw | diff to current
2013-07-09 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys blob | commitdiff | raw | diff to current
2013-07-09 Clifford WolfMajor redesign of expr width/sign detecion (verilog... blob | commitdiff | raw | diff to current
2013-07-04 Clifford WolfAdded defparam support to Verilog/AST frontend blob | commitdiff | raw | diff to current
2013-06-10 Clifford WolfEnabled AST/Verilog front-end optimizations per default blob | commitdiff | raw | diff to current
2013-05-16 Clifford WolfMerge branch 'bugfix' blob | commitdiff | raw | diff to current
2013-03-31 Clifford WolfNow only use value from "initial" when no matching... blob | commitdiff | raw | diff to current
2013-03-31 Clifford WolfAdded AST_INITIAL (before verilog "initial" was mapped... blob | commitdiff | raw | diff to current
2013-03-28 Clifford WolfImplemented proper handling of stub placeholder modules blob | commitdiff | raw | diff to current
2013-03-25 Clifford WolfAdded nosync attribute and some async reset related... blob | commitdiff | raw | diff to current
2013-03-24 Clifford WolfAdded mem2reg option to verilog frontend blob | commitdiff | raw | diff to current
2013-03-24 Clifford WolfImproved mem2reg handling in ast simplifier blob | commitdiff | raw | diff to current
2013-02-26 Clifford WolfAdded support for verilog genblock[index].member syntax blob | commitdiff | raw | diff to current
2013-01-05 Clifford Wolfinitial import blob | commitdiff | raw | diff to current