Make genvar a signed type
[yosys.git] / frontends / ast / genrtlil.cc
2019-06-20 Clifford WolfMerge branch 'unpacked_arrays' of https://github.com...
2019-06-19 Clifford WolfMerge pull request #1109 from YosysHQ/clifford/fix1106
2019-06-19 Clifford WolfAdd "read_verilog -pwires" feature, closes #1106
2019-06-13 Serge BazanskiMerge pull request #829 from abdelrahmanhosny/master
2019-06-08 Clifford WolfMerge pull request #1078 from YosysHQ/eddie/muxcover_costs
2019-06-07 Clifford WolfMerge pull request #1077 from YosysHQ/clifford/pr983
2019-06-07 Clifford WolfFixes and cleanups in AST_TECALL handling
2019-06-07 Clifford WolfMerge branch 'pr_elab_sys_tasks' of https://github...
2019-06-06 David ShahMerge pull request #1073 from whitequark/ecp5-diamond-iob
2019-06-05 Clifford WolfMerge pull request #999 from jakobwenzel/setundefInitFix
2019-05-28 Clifford WolfMerge pull request #1049 from YosysHQ/clifford/fix1047
2019-05-28 Clifford WolfMerge pull request #1050 from YosysHQ/clifford/wandwor
2019-05-28 Clifford WolfMerge branch 'wandwor' of https://github.com/thasti...
2019-05-27 Stefan BiereigelMerge branch 'master' into wandwor
2019-05-27 Stefan Biereigelmove wand/wor resolution into hierarchy pass
2019-05-27 Clifford WolfMerge pull request #1044 from mmicko/invalid_width_range
2019-05-27 Clifford WolfMerge pull request #1043 from mmicko/unsized_constant
2019-05-27 Miodrag MilanovicGive error instead of asserting for invalid range,...
2019-05-27 Miodrag MilanovicAdded support for unsized constants, fixes #1022
2019-05-23 Stefan Biereigelfix assignment of non-wires
2019-05-23 Stefan Biereigelfix indentation across files
2019-05-23 Stefan Biereigelimplementation for assignments working
2019-05-21 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-05-08 Clifford WolfMerge pull request #991 from kristofferkoch/gcc9-warnings
2019-05-06 Clifford WolfMerge pull request #946 from YosysHQ/clifford/specify
2019-05-06 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-05-06 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-05-04 Clifford WolfImprove write_verilog specify support
2019-05-03 Eddie HungMerge remote-tracking branch 'origin/master' into cliff...
2019-05-03 Clifford WolfMerge pull request #969 from YosysHQ/clifford/pmgenstuff
2019-05-03 Clifford WolfMerge pull request #984 from YosysHQ/eddie/fix_982
2019-05-03 Clifford WolfMerge pull request #976 from YosysHQ/clifford/fix974
2019-05-03 Udi FinkelsteinInitial implementation of elaboration system tasks
2019-05-01 Clifford WolfFix width detection of memory access with bit slice...
2019-04-23 Clifford WolfAdd $specrule cells for $setup/$hold/$skew specify...
2019-04-23 Clifford WolfChecking and fixing specify cells in genRTLIL
2019-04-01 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2019-03-19 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-03-14 Clifford WolfMerge pull request #872 from YosysHQ/clifford/pmuxfix
2019-03-14 Clifford WolfImprove handling of "full_case" attributes
2019-03-14 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-09 Clifford WolfMerge pull request #859 from smunaut/ice40_braminit
2019-03-09 Clifford WolfMerge pull request #858 from YosysHQ/clifford/svalabels
2019-03-07 Clifford WolfAdd support for SVA labels in read_verilog
2019-03-05 Clifford WolfMerge pull request #842 from litghost/merge_upstream
2019-03-05 Clifford WolfMerge pull request #850 from daveshah1/ecp5_warn_conflict
2019-03-04 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-03-03 Clifford WolfMerge pull request #848 from YosysHQ/clifford/fix763
2019-03-02 Clifford WolfFix error for wire decl in always block, fixes #763
2019-02-28 Clifford WolfMerge pull request #794 from daveshah1/ecp5improve
2019-02-26 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-02-24 Clifford WolfMerge pull request #812 from ucb-bar/arrayhierarchyfixes
2019-02-24 Clifford WolfMerge pull request #824 from litghost/fix_reduce_on_ff
2019-02-22 Clifford WolfMerge pull request #819 from YosysHQ/clifford/optd
2019-02-22 Clifford WolfMerge pull request #820 from YosysHQ/clifford/fix810
2019-02-22 Clifford WolfMerge pull request #740 from daveshah1/improve_dress
2019-02-21 Clifford WolfFixes related to handling of autowires and upto-ranges...
2019-02-21 Clifford WolfFix segfault in printing of some internal error messages
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into dff_init
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-02-17 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-02-15 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-02-13 Clifford WolfFix sign handling of real constants
2018-12-18 Jim LawsonMerge remote-tracking branch 'upstream/master'
2018-12-01 Clifford WolfMerge pull request #676 from rafaeltp/master
2018-11-12 Clifford WolfMerge pull request #695 from daveshah1/ecp5_bb
2018-11-04 Clifford WolfVarious indenting fixes in AST front-end (mostly space...
2018-10-25 Clifford WolfMerge pull request #679 from udif/pr_syntax_error
2018-10-23 Clifford WolfMerge pull request #677 from daveshah1/ecp5_dsp
2018-10-21 rafaeltpMerge pull request #1 from YosysHQ/master
2018-10-20 Clifford WolfImprove read_verilog range out of bounds warning
2018-10-20 Clifford WolfMerge pull request #674 from rubund/feature/svinterface...
2018-10-20 Ruben UndheimRefactor code to avoid code duplication + added comments
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram
2018-10-18 Clifford WolfMerge pull request #659 from rubund/sv_interfaces
2018-10-17 Clifford WolfMerge pull request #663 from aman-goel/master
2018-10-17 Clifford WolfMerge pull request #638 from udif/pr_reg_wire_error
2018-10-16 Clifford WolfMerge branch 'yosys-0.8-rc'
2018-10-13 Ruben UndheimDocumentation improvements etc.
2018-10-12 Ruben UndheimSupport for 'modports' for System Verilog interfaces
2018-10-12 Ruben UndheimSynthesis support for SystemVerilog interfaces
2018-10-08 Tom VerbeureFix for issue 594.
2018-10-05 Clifford WolfMerge pull request #651 from ARandomOWL/stdcells_fix
2018-10-03 tklamMerge branch 'master' of https://github.com/YosysHQ...
2018-10-02 Clifford WolfMerge pull request #645 from daveshah1/ecp5_dram_fix
2018-10-02 Clifford WolfMerge pull request #646 from tomverbeure/issue594
2018-10-02 Tom VerbeureFix for issue 594.
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #576 from cr1901/no-resource
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error
2018-08-15 Clifford WolfMerge pull request #562 from udif/pr_fix_illegal_port_decl
2018-07-20 Clifford WolfMerge pull request #586 from hzeller/more-sourcepos...
2018-07-20 Henner ZellerConvert more log_error() to log_file_error() where...
2018-07-20 Clifford WolfMerge pull request #585 from hzeller/use-file-warning...
2018-07-20 Henner ZellerUse log_file_warning(), log_file_error() functions.
next