Merge remote-tracking branch 'origin/master' into clifford/specify
[yosys.git] / frontends / ast / genrtlil.cc
2019-05-03 Eddie HungMerge remote-tracking branch 'origin/master' into cliff...
2019-05-03 Clifford WolfMerge pull request #969 from YosysHQ/clifford/pmgenstuff
2019-05-03 Clifford WolfMerge pull request #984 from YosysHQ/eddie/fix_982
2019-05-03 Clifford WolfMerge pull request #976 from YosysHQ/clifford/fix974
2019-05-01 Clifford WolfFix width detection of memory access with bit slice...
2019-04-23 Clifford WolfAdd $specrule cells for $setup/$hold/$skew specify...
2019-04-23 Clifford WolfChecking and fixing specify cells in genRTLIL
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2019-03-19 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-03-14 Clifford WolfMerge pull request #872 from YosysHQ/clifford/pmuxfix
2019-03-14 Clifford WolfImprove handling of "full_case" attributes
2019-03-14 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-09 Clifford WolfMerge pull request #859 from smunaut/ice40_braminit
2019-03-09 Clifford WolfMerge pull request #858 from YosysHQ/clifford/svalabels
2019-03-07 Clifford WolfAdd support for SVA labels in read_verilog
2019-03-05 Clifford WolfMerge pull request #842 from litghost/merge_upstream
2019-03-05 Clifford WolfMerge pull request #850 from daveshah1/ecp5_warn_conflict
2019-03-03 Clifford WolfMerge pull request #848 from YosysHQ/clifford/fix763
2019-03-02 Clifford WolfFix error for wire decl in always block, fixes #763
2019-02-28 Clifford WolfMerge pull request #794 from daveshah1/ecp5improve
2019-02-24 Clifford WolfMerge pull request #812 from ucb-bar/arrayhierarchyfixes
2019-02-24 Clifford WolfMerge pull request #824 from litghost/fix_reduce_on_ff
2019-02-22 Clifford WolfMerge pull request #819 from YosysHQ/clifford/optd
2019-02-22 Clifford WolfMerge pull request #820 from YosysHQ/clifford/fix810
2019-02-22 Clifford WolfMerge pull request #740 from daveshah1/improve_dress
2019-02-21 Clifford WolfFixes related to handling of autowires and upto-ranges...
2019-02-21 Clifford WolfFix segfault in printing of some internal error messages
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into dff_init
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-02-17 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-02-13 Clifford WolfFix sign handling of real constants
2018-12-01 Clifford WolfMerge pull request #676 from rafaeltp/master
2018-11-12 Clifford WolfMerge pull request #695 from daveshah1/ecp5_bb
2018-11-04 Clifford WolfVarious indenting fixes in AST front-end (mostly space...
2018-10-25 Clifford WolfMerge pull request #679 from udif/pr_syntax_error
2018-10-23 Clifford WolfMerge pull request #677 from daveshah1/ecp5_dsp
2018-10-21 rafaeltpMerge pull request #1 from YosysHQ/master
2018-10-20 Clifford WolfImprove read_verilog range out of bounds warning
2018-10-20 Clifford WolfMerge pull request #674 from rubund/feature/svinterface...
2018-10-20 Ruben UndheimRefactor code to avoid code duplication + added comments
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram
2018-10-18 Clifford WolfMerge pull request #659 from rubund/sv_interfaces
2018-10-17 Clifford WolfMerge pull request #663 from aman-goel/master
2018-10-17 Clifford WolfMerge pull request #638 from udif/pr_reg_wire_error
2018-10-16 Clifford WolfMerge branch 'yosys-0.8-rc'
2018-10-13 Ruben UndheimDocumentation improvements etc.
2018-10-12 Ruben UndheimSupport for 'modports' for System Verilog interfaces
2018-10-12 Ruben UndheimSynthesis support for SystemVerilog interfaces
2018-10-05 Clifford WolfMerge pull request #651 from ARandomOWL/stdcells_fix
2018-10-03 tklamMerge branch 'master' of https://github.com/YosysHQ...
2018-10-02 Clifford WolfMerge pull request #645 from daveshah1/ecp5_dram_fix
2018-10-02 Clifford WolfMerge pull request #646 from tomverbeure/issue594
2018-10-02 Tom VerbeureFix for issue 594.
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #576 from cr1901/no-resource
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error
2018-08-15 Clifford WolfMerge pull request #562 from udif/pr_fix_illegal_port_decl
2018-07-20 Clifford WolfMerge pull request #586 from hzeller/more-sourcepos...
2018-07-20 Henner ZellerConvert more log_error() to log_file_error() where...
2018-07-20 Clifford WolfMerge pull request #585 from hzeller/use-file-warning...
2018-07-20 Henner ZellerUse log_file_warning(), log_file_error() functions.
2018-07-20 Clifford WolfMerge pull request #584 from hzeller/provide-source...
2018-07-19 Henner ZellerProvide source-location logging.
2018-07-04 Aman GoelMerge branch 'YosysHQ-master'
2018-07-04 Aman GoelMerging with official repo
2018-06-28 Clifford WolfFix handling of signed memories
2018-06-01 Clifford WolfAdd (* gclk *) attribute support
2018-02-23 Clifford WolfMerge branch 'forall'
2018-02-23 Clifford WolfAdd $allconst and $allseq cell types
2017-12-09 Clifford WolfMerge branch 'master' into btor-ng
2017-12-02 Clifford WolfFix error handling for nested always/initial
2017-06-07 Clifford WolfFix generation of vlogtb output in yosys-smtbmc for...
2017-02-25 Clifford WolfMerge branch 'master' of https://github.com/klammerj...
2017-02-25 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-02-25 Clifford WolfAdd $live and $fair cell types, add support for s_event...
2017-02-11 Clifford WolfMerge branch 'master' of https://github.com/stv0g/yosys...
2017-02-09 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-04 Clifford WolfAdd $cover cell type and SVA cover() support
2016-11-01 Clifford WolfSome fixes in handling of signed arrays
2016-10-14 Clifford WolfAdded $anyseq cell type
2016-10-14 Clifford WolfAdded $global_clock verilog syntax support for creating...
2016-09-23 Clifford WolfMerge branch 'master' of https://github.com/brouhaha...
2016-09-18 Clifford WolfAdded $past, $stable, $rose, $fell SVA functions
2016-09-06 Clifford WolfAdded assertpmux
2016-08-30 Clifford WolfAdded $anyconst support to yosys-smtbmc
2016-08-30 Clifford WolfRemoved $aconst cell type
2016-08-28 Clifford WolfRemoved $predict again
2016-08-21 Clifford WolfAnother bugfix in mem2reg code
2016-08-19 Clifford WolfOptimize memory address port width in wreduce and memor...
2016-08-10 Clifford WolfOnly allow posedge/negedge with 1 bit wide signals
2016-07-30 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-07-27 Clifford WolfAdded $anyconst and $aconst
2016-07-21 Clifford WolfAfter reading the SV spec, using non-standard predict...
2016-07-13 Clifford WolfAdded basic support for $expect cells
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-06-19 Clifford WolfMerge branch 'sv_packages' of https://github.com/rubund...
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