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Merge remote-tracking branch 'origin/master' into clifford/specify
[yosys.git]
/
frontends
/
ast
/
genrtlil.cc
2019-05-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into cliff...
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2019-05-03
Clifford Wolf
Merge pull request #969 from YosysHQ/clifford/pmgenstuff
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2019-05-03
Clifford Wolf
Merge pull request #984 from YosysHQ/eddie/fix_982
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2019-05-03
Clifford Wolf
Merge pull request #976 from YosysHQ/clifford/fix974
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2019-05-01
Clifford Wolf
Fix width detection of memory access with bit slice...
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2019-04-23
Clifford Wolf
Add $specrule cells for $setup/$hold/$skew specify...
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2019-04-23
Clifford Wolf
Checking and fixing specify cells in genRTLIL
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2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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2019-03-19
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-19
Eddie Hung
Merge https://github.com/YosysHQ/yosys into read_aiger
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2019-03-14
Clifford Wolf
Merge pull request #872 from YosysHQ/clifford/pmuxfix
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2019-03-14
Clifford Wolf
Improve handling of "full_case" attributes
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2019-03-14
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-09
Clifford Wolf
Merge pull request #859 from smunaut/ice40_braminit
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2019-03-09
Clifford Wolf
Merge pull request #858 from YosysHQ/clifford/svalabels
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2019-03-07
Clifford Wolf
Add support for SVA labels in read_verilog
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2019-03-05
Clifford Wolf
Merge pull request #842 from litghost/merge_upstream
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2019-03-05
Clifford Wolf
Merge pull request #850 from daveshah1/ecp5_warn_conflict
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2019-03-03
Clifford Wolf
Merge pull request #848 from YosysHQ/clifford/fix763
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2019-03-02
Clifford Wolf
Fix error for wire decl in always block, fixes #763
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2019-02-28
Clifford Wolf
Merge pull request #794 from daveshah1/ecp5improve
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2019-02-24
Clifford Wolf
Merge pull request #812 from ucb-bar/arrayhierarchyfixes
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2019-02-24
Clifford Wolf
Merge pull request #824 from litghost/fix_reduce_on_ff
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2019-02-22
Clifford Wolf
Merge pull request #819 from YosysHQ/clifford/optd
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2019-02-22
Clifford Wolf
Merge pull request #820 from YosysHQ/clifford/fix810
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2019-02-22
Clifford Wolf
Merge pull request #740 from daveshah1/improve_dress
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2019-02-21
Clifford Wolf
Fixes related to handling of autowires and upto-ranges...
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2019-02-21
Clifford Wolf
Fix segfault in printing of some internal error messages
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2019-02-17
Eddie Hung
Merge https://github.com/YosysHQ/yosys into dff_init
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2019-02-17
Eddie Hung
Merge https://github.com/YosysHQ/yosys into read_aiger
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2019-02-17
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys into...
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2019-02-13
Clifford Wolf
Fix sign handling of real constants
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2018-12-01
Clifford Wolf
Merge pull request #676 from rafaeltp/master
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2018-11-12
Clifford Wolf
Merge pull request #695 from daveshah1/ecp5_bb
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2018-11-04
Clifford Wolf
Various indenting fixes in AST front-end (mostly space...
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2018-10-25
Clifford Wolf
Merge pull request #679 from udif/pr_syntax_error
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2018-10-23
Clifford Wolf
Merge pull request #677 from daveshah1/ecp5_dsp
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2018-10-21
rafaeltp
Merge pull request #1 from YosysHQ/master
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2018-10-20
Clifford Wolf
Improve read_verilog range out of bounds warning
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2018-10-20
Clifford Wolf
Merge pull request #674 from rubund/feature/svinterface...
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2018-10-20
Ruben Undheim
Refactor code to avoid code duplication + added comments
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2018-10-19
Clifford Wolf
Merge pull request #672 from daveshah1/fix_bram
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2018-10-18
Clifford Wolf
Merge pull request #659 from rubund/sv_interfaces
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2018-10-17
Clifford Wolf
Merge pull request #663 from aman-goel/master
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2018-10-17
Clifford Wolf
Merge pull request #638 from udif/pr_reg_wire_error
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2018-10-16
Clifford Wolf
Merge branch 'yosys-0.8-rc'
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2018-10-13
Ruben Undheim
Documentation improvements etc.
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2018-10-12
Ruben Undheim
Support for 'modports' for System Verilog interfaces
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2018-10-12
Ruben Undheim
Synthesis support for SystemVerilog interfaces
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2018-10-05
Clifford Wolf
Merge pull request #651 from ARandomOWL/stdcells_fix
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2018-10-03
tklam
Merge branch 'master' of https://github.com/YosysHQ...
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2018-10-02
Clifford Wolf
Merge pull request #645 from daveshah1/ecp5_dram_fix
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2018-10-02
Clifford Wolf
Merge pull request #646 from tomverbeure/issue594
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2018-10-02
Tom Verbeure
Fix for issue 594.
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
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2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
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2018-08-15
Clifford Wolf
Merge pull request #576 from cr1901/no-resource
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2018-08-15
Clifford Wolf
Merge pull request #513 from udif/pr_reg_wire_error
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2018-08-15
Clifford Wolf
Merge pull request #562 from udif/pr_fix_illegal_port_decl
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2018-07-20
Clifford Wolf
Merge pull request #586 from hzeller/more-sourcepos...
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2018-07-20
Henner Zeller
Convert more log_error() to log_file_error() where...
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2018-07-20
Clifford Wolf
Merge pull request #585 from hzeller/use-file-warning...
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2018-07-20
Henner Zeller
Use log_file_warning(), log_file_error() functions.
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2018-07-20
Clifford Wolf
Merge pull request #584 from hzeller/provide-source...
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2018-07-19
Henner Zeller
Provide source-location logging.
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2018-07-04
Aman Goel
Merge branch 'YosysHQ-master'
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2018-07-04
Aman Goel
Merging with official repo
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2018-06-28
Clifford Wolf
Fix handling of signed memories
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2018-06-01
Clifford Wolf
Add (* gclk *) attribute support
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2018-02-23
Clifford Wolf
Merge branch 'forall'
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2018-02-23
Clifford Wolf
Add $allconst and $allseq cell types
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2017-12-09
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-12-02
Clifford Wolf
Fix error handling for nested always/initial
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2017-06-07
Clifford Wolf
Fix generation of vlogtb output in yosys-smtbmc for...
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2017-02-25
Clifford Wolf
Merge branch 'master' of https://github.com/klammerj...
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2017-02-25
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-02-25
Clifford Wolf
Add $live and $fair cell types, add support for s_event...
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2017-02-11
Clifford Wolf
Merge branch 'master' of https://github.com/stv0g/yosys...
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2017-02-09
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2017-02-04
Clifford Wolf
Add $cover cell type and SVA cover() support
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2016-11-01
Clifford Wolf
Some fixes in handling of signed arrays
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2016-10-14
Clifford Wolf
Added $anyseq cell type
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2016-10-14
Clifford Wolf
Added $global_clock verilog syntax support for creating...
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2016-09-23
Clifford Wolf
Merge branch 'master' of https://github.com/brouhaha...
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2016-09-18
Clifford Wolf
Added $past, $stable, $rose, $fell SVA functions
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2016-09-06
Clifford Wolf
Added assertpmux
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2016-08-30
Clifford Wolf
Added $anyconst support to yosys-smtbmc
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2016-08-30
Clifford Wolf
Removed $aconst cell type
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2016-08-28
Clifford Wolf
Removed $predict again
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2016-08-21
Clifford Wolf
Another bugfix in mem2reg code
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2016-08-19
Clifford Wolf
Optimize memory address port width in wreduce and memor...
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2016-08-10
Clifford Wolf
Only allow posedge/negedge with 1 bit wide signals
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2016-07-30
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-07-27
Clifford Wolf
Added $anyconst and $aconst
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2016-07-21
Clifford Wolf
After reading the SV spec, using non-standard predict...
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2016-07-13
Clifford Wolf
Added basic support for $expect cells
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-06-19
Clifford Wolf
Merge branch 'sv_packages' of https://github.com/rubund...
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