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[yosys.git] / frontends / ast / genrtlil.cc

2014-12-24	Clifford Wolf	Renamed extend() to extend_xx(), changed most users...	blob \| commitdiff \| raw
2014-11-09	Clifford Wolf	Added log_warning() API	blob \| commitdiff \| raw \| diff to current
2014-10-10	Clifford Wolf	Renamed SIZE() to GetSize() because of name collision...	blob \| commitdiff \| raw \| diff to current
2014-09-22	Ahmed Irfan	Merge branch 'master' of https://github.com/cliffordwol...	blob \| commitdiff \| raw \| diff to current
2014-09-06	Clifford Wolf	Fixed assignment of out-of bounds array element	blob \| commitdiff \| raw \| diff to current
2014-09-04	Clifford Wolf	Removed $bu0 cell type	blob \| commitdiff \| raw \| diff to current
2014-08-21	Clifford Wolf	Merge branch 'master' of github.com:cliffordwolf/yosys	blob \| commitdiff \| raw \| diff to current
2014-08-21	Clifford Wolf	Added Verilog/AST support for DPI functions (dpi_call...	blob \| commitdiff \| raw \| diff to current
2014-08-17	Clifford Wolf	Improved AST ProcessGenerator performance	blob \| commitdiff \| raw \| diff to current
2014-08-16	Clifford Wolf	Use stackmap<> in AST ProcessGenerator	blob \| commitdiff \| raw \| diff to current
2014-08-16	Clifford Wolf	AST ProcessGenerator: replaced subst_*_{from,to} with...	blob \| commitdiff \| raw \| diff to current
2014-08-14	Clifford Wolf	Added RTLIL::SigSpec::to_sigbit_map()	blob \| commitdiff \| raw \| diff to current
2014-08-14	Clifford Wolf	Changed the AST genWidthRTLIL subst interface to use...	blob \| commitdiff \| raw \| diff to current
2014-08-02	Clifford Wolf	More cleanups related to RTLIL::IdString usage	blob \| commitdiff \| raw \| diff to current
2014-07-31	Clifford Wolf	Renamed port access function on RTLIL::Cell, added...	blob \| commitdiff \| raw \| diff to current
2014-07-31	Clifford Wolf	Moved some stuff to kernel/yosys.{h,cc}, using Yosys...	blob \| commitdiff \| raw \| diff to current
2014-07-29	Clifford Wolf	Added $shift and $shiftx cell types (needed for correct...	blob \| commitdiff \| raw \| diff to current
2014-07-28	Clifford Wolf	Removed left over debug code	blob \| commitdiff \| raw \| diff to current
2014-07-28	Clifford Wolf	Fixed part selects of parameters	blob \| commitdiff \| raw \| diff to current
2014-07-28	Clifford Wolf	Set results of out-of-bounds static bit/part select...	blob \| commitdiff \| raw \| diff to current
2014-07-28	Clifford Wolf	Fixed RTLIL code generator for part select of parameter	blob \| commitdiff \| raw \| diff to current
2014-07-28	Clifford Wolf	Fixed width detection for part selects	blob \| commitdiff \| raw \| diff to current
2014-07-28	Clifford Wolf	Added support for "upto" wires to Verilog front- and...	blob \| commitdiff \| raw \| diff to current
2014-07-28	Clifford Wolf	Added wire->upto flag for signals such as "wire [0...	blob \| commitdiff \| raw \| diff to current
2014-07-28	Clifford Wolf	Using log_assert() instead of assert()	blob \| commitdiff \| raw \| diff to current
2014-07-28	Clifford Wolf	Fixed signdness detection of expressions with bit-...	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Refactoring: Renamed RTLIL::Module::wires to wires_	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Changed a lot of code to the new RTLIL::Wire constructors	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Merge automatic and manual code changes for new cell...	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Manual fixes for new cell connections API	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Changed users of cell->connections_ to the new API...	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Renamed RTLIL::{Module,Cell}::connections to connections_	blob \| commitdiff \| raw \| diff to current
2014-07-25	Clifford Wolf	Use only module->addCell() and module->remove() to...	blob \| commitdiff \| raw \| diff to current
2014-07-24	Clifford Wolf	Replaced more old SigChunk programming patterns	blob \| commitdiff \| raw \| diff to current
2014-07-23	Clifford Wolf	Removed RTLIL::SigSpec::optimize()	blob \| commitdiff \| raw \| diff to current
2014-07-22	Clifford Wolf	SigSpec refactoring: More cleanups of old SigSpec use...	blob \| commitdiff \| raw \| diff to current
2014-07-22	Clifford Wolf	SigSpec refactoring: change RTLIL::SigSpec::chunks...	blob \| commitdiff \| raw \| diff to current
2014-07-22	Clifford Wolf	SigSpec refactoring: change RTLIL::SigSpec::size()...	blob \| commitdiff \| raw \| diff to current
2014-07-22	Clifford Wolf	SigSpec refactoring: using the accessor functions every...	blob \| commitdiff \| raw \| diff to current
2014-07-22	Clifford Wolf	SigSpec refactoring: renamed chunks and width to __chun...	blob \| commitdiff \| raw \| diff to current
2014-07-16	Clifford Wolf	Merged new $mem/$memwr WR_EN interface	blob \| commitdiff \| raw \| diff to current
2014-07-16	Clifford Wolf	changes in verilog frontend for new $mem/$memwr WR_EN...	blob \| commitdiff \| raw \| diff to current
2014-06-24	Clifford Wolf	More found_real-related fixes to AstNode::detectSignWid...	blob \| commitdiff \| raw \| diff to current
2014-06-21	Clifford Wolf	fixed signdness detection for expressions with reals	blob \| commitdiff \| raw \| diff to current
2014-06-16	Clifford Wolf	Added found_real feature to AstNode::detectSignWidth	blob \| commitdiff \| raw \| diff to current
2014-06-14	Clifford Wolf	improved (fixed) conversion of real values to bit vectors	blob \| commitdiff \| raw \| diff to current
2014-06-14	Clifford Wolf	Added real->int convertion in ast genrtlil	blob \| commitdiff \| raw \| diff to current
2014-06-06	Clifford Wolf	further improved const function support	blob \| commitdiff \| raw \| diff to current
2014-06-06	Clifford Wolf	improved const function support	blob \| commitdiff \| raw \| diff to current
2014-02-26	Clifford Wolf	Fixed bit-extending in $mux argument (use $bu0 instead...	blob \| commitdiff \| raw \| diff to current
2014-02-24	Clifford Wolf	Don't blow up constants unneccessarily in Verilog frontend	blob \| commitdiff \| raw \| diff to current
2014-02-17	Clifford Wolf	Added Verilog support for "`default_nettype none"	blob \| commitdiff \| raw \| diff to current
2014-02-15	Clifford Wolf	Correctly convert constants to RTLIL (fixed undef handling)	blob \| commitdiff \| raw \| diff to current
2014-02-14	Clifford Wolf	Created basic support for function calls in parameter...	blob \| commitdiff \| raw \| diff to current
2014-02-03	Clifford Wolf	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARE...	blob \| commitdiff \| raw \| diff to current
2014-02-01	Clifford Wolf	Added constant size expression support of sized constants	blob \| commitdiff \| raw \| diff to current
2014-01-28	Clifford Wolf	Added read_verilog -icells option	blob \| commitdiff \| raw \| diff to current
2014-01-20	Ahmed Irfan	Merge branch 'master' of https://github.com/cliffordwol...	blob \| commitdiff \| raw \| diff to current
2014-01-19	Clifford Wolf	Added $assert cell	blob \| commitdiff \| raw \| diff to current
2014-01-03	Ahmed Irfan	Merge branch 'master' of https://github.com/cliffordwol...	blob \| commitdiff \| raw \| diff to current
2014-01-02	Clifford Wolf	Added correct handling of $memwr priority	blob \| commitdiff \| raw \| diff to current
2013-12-27	Clifford Wolf	Added support for non-const === and !== (for miter...	blob \| commitdiff \| raw \| diff to current
2013-12-27	Clifford Wolf	Added proper === and !== support in constant expressions	blob \| commitdiff \| raw \| diff to current
2013-12-04	Clifford Wolf	Various improvements in support for generate statements	blob \| commitdiff \| raw \| diff to current
2013-12-04	Clifford Wolf	Replaced signed_parameters API with CONST_FLAG_SIGNED	blob \| commitdiff \| raw \| diff to current
2013-12-04	Clifford Wolf	Replaced RTLIL::Const::str with generic decoder method	blob \| commitdiff \| raw \| diff to current
2013-12-04	Clifford Wolf	Added support for local regs in named blocks	blob \| commitdiff \| raw \| diff to current
2013-11-28	Clifford Wolf	Merge pull request #17 from mschmoelzer/master	blob \| commitdiff \| raw \| diff to current
2013-11-28	Clifford Wolf	Fixed temp net name generation in rtlil process generat...	blob \| commitdiff \| raw \| diff to current
2013-11-28	Clifford Wolf	Added "src" attribute to processes	blob \| commitdiff \| raw \| diff to current
2013-11-24	Clifford Wolf	Added module->avail_parameters (for advanced techmap...	blob \| commitdiff \| raw \| diff to current
2013-11-24	Clifford Wolf	Remove auto_wire framework (smarter than the verilog...	blob \| commitdiff \| raw \| diff to current
2013-11-24	Clifford Wolf	Implemented correct handling of signed module parameters	blob \| commitdiff \| raw \| diff to current
2013-11-21	Clifford Wolf	Major improvements in mem2reg and added "init" sync...	blob \| commitdiff \| raw \| diff to current
2013-11-18	Clifford Wolf	Fixed parsing of default cases when not last case	blob \| commitdiff \| raw \| diff to current
2013-11-10	Clifford Wolf	Cleanups and bugfixes in response to new internal cell...	blob \| commitdiff \| raw \| diff to current
2013-11-08	Clifford Wolf	More undef-propagation related fixes	blob \| commitdiff \| raw \| diff to current
2013-11-07	Clifford Wolf	Fixed handling of power operator	blob \| commitdiff \| raw \| diff to current
2013-11-07	Clifford Wolf	Fixed more extend vs. extend_u0 issues	blob \| commitdiff \| raw \| diff to current
2013-11-07	Clifford Wolf	Renamed extend_un0() to extend_u0() and use it in genrtlil	blob \| commitdiff \| raw \| diff to current
2013-11-07	Clifford Wolf	Fixed const folding in corner cases with parameters	blob \| commitdiff \| raw \| diff to current
2013-11-07	Clifford Wolf	Fixed width detection for replicate operator	blob \| commitdiff \| raw \| diff to current
2013-11-07	Clifford Wolf	Various fixes for correct parameter support	blob \| commitdiff \| raw \| diff to current
2013-11-07	Clifford Wolf	Fixed the fix for propagation of width hints for $signe...	blob \| commitdiff \| raw \| diff to current
2013-11-06	Clifford Wolf	Fixed propagation of width hints for $signed() and...	blob \| commitdiff \| raw \| diff to current
2013-11-06	Clifford Wolf	Additional fixes for undef propagation in concat and...	blob \| commitdiff \| raw \| diff to current
2013-11-06	Clifford Wolf	Improved width extension with regard to undef propagation	blob \| commitdiff \| raw \| diff to current
2013-11-04	Clifford Wolf	further improved early width and sign detection in...	blob \| commitdiff \| raw \| diff to current
2013-11-03	Clifford Wolf	Merge branch 'master' of github.com:cliffordwolf/yosys	blob \| commitdiff \| raw \| diff to current
2013-11-03	Clifford Wolf	Fixed detectSignWidthWorker (ast frontend) for AST_CONCAT	blob \| commitdiff \| raw \| diff to current
2013-11-02	Clifford Wolf	Behavior should be identical now to rev. 0b4a64ac6adbd6...	blob \| commitdiff \| raw \| diff to current
2013-11-02	Clifford Wolf	Various ast changes for early expression width detectio...	blob \| commitdiff \| raw \| diff to current
2013-10-24	Clifford Wolf	Fixed handling of boolean attributes (frontends)	blob \| commitdiff \| raw \| diff to current
2013-08-19	Clifford Wolf	Fixed width and sign detection for ** operator	blob \| commitdiff \| raw \| diff to current
2013-08-12	Clifford Wolf	Added support for "2**n" shifter encoding	blob \| commitdiff \| raw \| diff to current
2013-08-09	Clifford Wolf	Added $div and $mod technology mapping	blob \| commitdiff \| raw \| diff to current
2013-07-12	Clifford Wolf	More fixes in ternary op sign handling	blob \| commitdiff \| raw \| diff to current
2013-07-11	Clifford Wolf	Fixed sign handling in ternary operator	blob \| commitdiff \| raw \| diff to current
2013-07-11	Clifford Wolf	Another vloghammer related bugfix	blob \| commitdiff \| raw \| diff to current
2013-07-09	Clifford Wolf	Fixed sign propagation in bit-wise operators	blob \| commitdiff \| raw \| diff to current
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