Implemented part/bit select on memory read
[yosys.git] / frontends / ast / simplify.cc
2013-11-20 Clifford WolfImplemented part/bit select on memory read
2013-11-18 Clifford WolfFixed two bugs in mem2reg functionality in AST frontend
2013-11-18 Clifford WolfFixed mem2reg for reg usage outside always block
2013-11-08 Clifford WolfFixed handling of different signedness in power operands
2013-11-08 Clifford WolfImplemented const folding of ternary op with undef...
2013-11-07 Clifford WolfFixed handling of power operator
2013-11-07 Clifford WolfFixed more extend vs. extend_u0 issues
2013-11-07 Clifford WolfDisabled const folding of ternary op when select is...
2013-11-07 Clifford WolfFixed sign handling in constants
2013-11-07 Clifford WolfFixed const folding in corner cases with parameters
2013-11-07 Clifford WolfFixed at_zero evaluation of dynamic ranges
2013-11-07 Clifford WolfVarious fixes for correct parameter support
2013-11-04 Clifford WolfAnother fix for early width and sign detection in ast...
2013-11-04 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-11-04 Clifford WolfFixed const folding of ternary operator
2013-11-04 Clifford WolfUse proper bit width ans sign extension for const folding
2013-11-04 Clifford WolfFixes for early width and sign detection in ast simplifier
2013-11-04 Clifford Wolffurther improved early width and sign detection in...
2013-11-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-11-02 Clifford WolfBehavior should be identical now to rev. 0b4a64ac6adbd6...
2013-11-02 Clifford WolfVarious ast changes for early expression width detectio...
2013-10-24 Clifford WolfFixed handling of boolean attributes (frontends)
2013-08-20 Clifford WolfMerge pull request #8 from hansiglaser/master
2013-08-20 Johann GlaserAdded support for notif0/notif1 primitives
2013-08-19 Clifford WolfAdded support for bufif0/bufif1 primitives
2013-08-19 Clifford WolfImproved ast dumping (ast/verilog frontend)
2013-07-04 Clifford WolfAdded defparam support to Verilog/AST frontend
2013-06-10 Clifford WolfFixes and improvements in AST const folding
2013-06-10 Clifford WolfEnabled AST/Verilog front-end optimizations per default
2013-05-16 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-05-16 Clifford WolfMerge branch 'bugfix'
2013-05-16 Clifford WolfFixed synthesis of functions in latched blocks
2013-03-31 Clifford WolfAdded AST_INITIAL (before verilog "initial" was mapped...
2013-03-26 Clifford WolfImprovements and bugfixes for generate blocks with...
2013-03-26 Clifford WolfFixed handling of unconditional generate blocks
2013-03-25 Clifford WolfAdded nosync attribute and some async reset related...
2013-03-24 Clifford WolfAdded mem2reg option to verilog frontend
2013-03-24 Clifford WolfAnother fix in mem2reg ast simplify logic
2013-03-24 Clifford WolfImproved mem2reg handling in ast simplifier
2013-03-23 Clifford WolfTiny fixes to verilog parser
2013-02-27 Clifford WolfMoved stand-alone libs to libs/ directory and added...
2013-02-26 Clifford WolfAdded support for verilog genblock[index].member syntax
2013-01-05 Clifford Wolfinitial import