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Fixed sign handling in constants
[yosys.git]
/
frontends
/
ast
/
simplify.cc
2013-11-07
Clifford Wolf
Fixed sign handling in constants
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2013-11-07
Clifford Wolf
Fixed const folding in corner cases with parameters
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2013-11-07
Clifford Wolf
Fixed at_zero evaluation of dynamic ranges
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2013-11-07
Clifford Wolf
Various fixes for correct parameter support
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2013-11-04
Clifford Wolf
Another fix for early width and sign detection in ast...
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2013-11-04
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2013-11-04
Clifford Wolf
Fixed const folding of ternary operator
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2013-11-04
Clifford Wolf
Use proper bit width ans sign extension for const folding
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2013-11-04
Clifford Wolf
Fixes for early width and sign detection in ast simplifier
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2013-11-04
Clifford Wolf
further improved early width and sign detection in...
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2013-11-03
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2013-11-02
Clifford Wolf
Behavior should be identical now to rev. 0b4a64ac6adbd6...
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2013-11-02
Clifford Wolf
Various ast changes for early expression width detectio...
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2013-10-24
Clifford Wolf
Fixed handling of boolean attributes (frontends)
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2013-08-20
Clifford Wolf
Merge pull request #8 from hansiglaser/master
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2013-08-20
Johann Glaser
Added support for notif0/notif1 primitives
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2013-08-19
Clifford Wolf
Added support for bufif0/bufif1 primitives
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2013-08-19
Clifford Wolf
Improved ast dumping (ast/verilog frontend)
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2013-07-04
Clifford Wolf
Added defparam support to Verilog/AST frontend
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2013-06-10
Clifford Wolf
Fixes and improvements in AST const folding
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2013-06-10
Clifford Wolf
Enabled AST/Verilog front-end optimizations per default
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2013-05-16
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2013-05-16
Clifford Wolf
Merge branch 'bugfix'
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2013-05-16
Clifford Wolf
Fixed synthesis of functions in latched blocks
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2013-03-31
Clifford Wolf
Added AST_INITIAL (before verilog "initial" was mapped...
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2013-03-26
Clifford Wolf
Improvements and bugfixes for generate blocks with...
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2013-03-26
Clifford Wolf
Fixed handling of unconditional generate blocks
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2013-03-25
Clifford Wolf
Added nosync attribute and some async reset related...
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2013-03-24
Clifford Wolf
Added mem2reg option to verilog frontend
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2013-03-24
Clifford Wolf
Another fix in mem2reg ast simplify logic
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2013-03-24
Clifford Wolf
Improved mem2reg handling in ast simplifier
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2013-03-23
Clifford Wolf
Tiny fixes to verilog parser
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2013-02-27
Clifford Wolf
Moved stand-alone libs to libs/ directory and added...
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2013-02-26
Clifford Wolf
Added support for verilog genblock[index].member syntax
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2013-01-05
Clifford Wolf
initial import
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